search for: preds

Displaying 20 results from an estimated 2272 matches for "preds".

2006 Dec 04
2
[LLVMdev] problem using scc_iterator on CallGraph
...ID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:32:32" target endian = little target pointersize = 32 target triple = "i686-pc-linux-gnu" implementation ; Functions: void %execute() { entry: br bool false, label %bb688, label %cond_true cond_true: ; preds = %entry ret void bb: ; preds = %bb688 switch int 0, label %bb684 [ int 33, label %bb412 int 35, label %bb604 int 37, label %bb531 int 38, label %bb418 int 42, label %bb495 int 43, label %bb467 int 45, label %cond_true484 int 47, label %bb510 int 48, label %bb408 i...
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to
2006 Dec 04
0
[LLVMdev] problem using scc_iterator on CallGraph
...datalayout = "e-p:32:32" > target endian = little > target pointersize = 32 > target triple = "i686-pc-linux-gnu" > > implementation ; Functions: > > void %execute() { > entry: > br bool false, label %bb688, label %cond_true > > cond_true: ; preds = %entry > ret void > > bb: ; preds = %bb688 > switch int 0, label %bb684 [ > int 33, label %bb412 > int 35, label %bb604 > int 37, label %bb531 > int 38, label %bb418 > int 42, label %bb495 > int 43, label %bb467 > int 45, label %cond_true48...
2006 Dec 04
1
[LLVMdev] problem using scc_iterator on CallGraph
...>>target endian = little >>target pointersize = 32 >>target triple = "i686-pc-linux-gnu" >> >>implementation ; Functions: >> >>void %execute() { >>entry: >> br bool false, label %bb688, label %cond_true >> >>cond_true: ; preds = %entry >> ret void >> >>bb: ; preds = %bb688 >> switch int 0, label %bb684 [ >> int 33, label %bb412 >> int 35, label %bb604 >> int 37, label %bb531 >> int 38, label %bb418 >> int 42, label %bb495 >> int 43, label %bb467 &gt...
2004 Dec 01
1
tuning SVM's
Hi I am doing this sort of thing: POLY: > > obj = best.tune(svm, similarity ~., data = training, kernel = "polynomial") > summary(obj) Call: best.tune(svm, similarity ~ ., data = training, kernel = "polynomial") Parameters: SVM-Type: eps-regression SVM-Kernel: polynomial cost: 1 degree: 3 gamma: 0.04545455 coef.0: 0
2008 Jul 17
0
[PATCH 17/29] ia64/pv_ops/xen: define xen paravirtualized instructions for hand written assembly code
define xen paravirtualized instructions for hand written assembly code. Signed-off-by: Yaozu (Eddie) Dong <eddie.dong at intel.com> Signed-off-by: Isaku Yamahata <yamahata at valinux.co.jp> Cc: Akio Takebe <takebe_akio at jp.fujitsu.com> --- include/asm-ia64/xen/inst.h | 447 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 447 insertions(+), 0 deletions(-) create
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
Hi, I’m facing a crash issue (--target=arm-linux-gnueabi -march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I found that an intended branch was not taken due to bad code generation after the Post RA Scheduler pass. A CMPri instruction after an INLINEASM block (which inturn contains a cmp, bne instruction) is being moved before the INLINEASM block incorrectly resulting in two
2010 Aug 11
1
[LLVMdev] Need advice on writing scheduling pass
Hello LLVM developers, I have a few questions regarding the passes that are run after instruction selection and before register allocation. I am writing a scheduling pass (modulo scheduling). Before I ask my questions, I will first try to explain the approach I am taking. - Currently, I am running the passes in the following order. (-debug-pass=Structure output) Remove unreachable machine
2006 Mar 05
1
predicted values in mgcv gam
Hi, In fitting GAMs to assess environmental preferences, I use the part of the fit where the lower confidence interval is above zero as my criterion for positive association between the environmental variable and species abundance. However I like to plot this on the original scale of species abundance. To do so I extract the fit and SE using predict.gam. Lately I compared more
2012 Dec 11
1
Rprof causing R to crash
I'm trying to use Rprof() to identify bottlenecks and speed up a particullary slow section of code which reads in a portion of a tif file and compares each of the values to values of predictors used for model fitting. I've written up an example that anyone can run. Generally temp would be a section of a tif read into a data.frame and used later for other processing. The first portion
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,
2010 May 26
1
how to Store loop output from a function
HI, Dear R community, I am writing the following function to create one data set(*tree.pred*) and one vector(*valid.out*) from loops. Later, I want to use the data set from this loop to plot curves. I have tried return, list, but I can not use the *tree.pred* data and *valid.out* vector. auc.tree<- function(msplit,mbucket) { * tree.pred<-data.frame()
2009 Jul 30
3
for loop for file names
I am trying to load binary files in the following fashion load("pred/Pred_pres_a_indpdt") load("pred/Pred_pres_b_indpdt") load("pred/Pred_pres_c_indpdt") load("pred/Pred_pres_d_indpdt") load("pred/Pred_pres_e_indpdt") load("pred/Pred_pres_f_indpdt") but I would like to set up a for loop to replace the letters a:f Here is what I have so
2010 Sep 05
2
[LLVMdev] Possible missed optimization?
On Sep 4, 2010, at 5:40 PM, Eli Friedman wrote: > If you want to take a look at this yourself, the issue is easy to > reproduce with Thumb1: Thanks, Eli. Nice catch! This IR: target triple = "thumbv5-u-u" define arm_aapcscc i64 @foo(i64 %a, i64 %b) nounwind readnone { entry: %xor = xor i64 %a, 18 ; <i64> [#uses=1] %xor2 = xor i64 %xor, %b
2015 Jul 16
3
[LLVMdev] why LoopUnswitch pass does not constant fold conditional branch and merge blocks
...@some_func() noreturn After running it through "opt -loop-unswitch -S", it unswitched loop on %cond and produced result like this: define i32 @test(i1 %cond) { br i1 %cond, label %..split_crit_edge, label %.loop_exit.split_crit_edge .loop_exit.split_crit_edge: ; preds = %0 br label %loop_exit.split ..split_crit_edge: ; preds = %0 br label %.split .split: ; preds = %..split_crit_edge br label %loop_begin loop_begin: ; preds = %do_something, %.sp...
2013 Jul 23
2
[LLVMdev] Question on optimizeThumb2JumpTables
In looking at the code in ARMConstantislandPass.cpp::optimizeThumb2JumpTables(), I see that there is the following condition for not creating tbb-based jump tables: // The instruction should be a tLEApcrel or t2LEApcrelJT; we want // to delete it as well. MachineInstr *LeaMI = PrevI; if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
2010 Sep 05
0
[LLVMdev] Possible missed optimization?
On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > >> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer
2011 Feb 01
0
[LLVMdev] Loop simplification
Here's what I've got so far - it seems to work, aside from the fact that DeleteDeadPHIs is not removing at least one dead PHI in my test program. --------------------- static bool mergeBlockIntoSuccessor(BasicBlock *pred, BasicBlock *succ) { if (succ == pred) return false; if (pred->getFirstNonPHI() != pred->getTerminator()) return false; //
2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]
2009 Sep 03
2
[LLVMdev] Non-local DSE optimization
...able > } > > declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind > > define fastcc void @c974001__lengthy_calculation. > 1736(%struct.FRAME.c974001* nocapture %CHAIN.185) noreturn { > entry: > br label %bb > > bb: ; preds = %bb, > %entry > br label %bb > } > > define fastcc void > @c974001__timed_calculation__calculation__B19b__B21b__A17b___clean. > 1830(%struct.FRAME.c974001__timed_calculation__calculationA* %CHAIN. > 188) { > entry: > ret void > } > > define fastcc vo...