search for: predreg1

...tReg0 is r3 ; CHECK: [[IntReg1:r[0-9]+]] = memb //IntReg1 is r4 ; CHECK-NOT: {{r[0-9]+}} = zxtb([[IntReg1]]) //Ensure no zxtb instructions exist between the loads and their uses. ; CHECK-NOT: {{r[0-9]+}} = zxtb([[IntReg0]]) ; CHECK: [[PredReg0:p[0-3]+]] = [[IntReg0]] // <--- [1] ; CHECK: [[PredReg1:p[0-3]+]] = [[IntReg1]] // <--- [2] ; CHECK: or([[PredReg1]], [[PredReg0]]) When I was trying to write this testcase I had thought that if the order of [1] and [2] changed because of some change in the scheduler, the optimization (removal of zxtb) would still hold, but the changed order would...

...tReg1:r[0-9]+]] = memb //IntReg1 is r4 > ; CHECK-NOT: {{r[0-9]+}} = zxtb([[IntReg1]]) //Ensure no zxtb > instructions exist between the loads and their uses. > ; CHECK-NOT: {{r[0-9]+}} = zxtb([[IntReg0]]) > ; CHECK: [[PredReg0:p[0-3]+]] = [[IntReg0]] // <--- [1] > ; CHECK: [[PredReg1:p[0-3]+]] = [[IntReg1]] // <--- [2] > ; CHECK: or([[PredReg1]], [[PredReg0]]) > > When I was trying to write this testcase I had thought that if the order > of [1] and [2] changed because of some change in the scheduler, the > optimization (removal of zxtb) would still hold, but...

On Thu, Sep 13, 2012 at 1:14 PM, Pranav Bhandarkar <pranavb at codeaurora.org>wrote: > Just adding to the clamor for FileChecks ability to pattern match > out-of-order (match for mere presence); Just in the last 2 weeks, I have > come across at least a couple instances when I was unable to add small unit > tests to the testsuite because of this deficiency in FileCheck. Also, I

Just adding to the clamor for FileChecks ability to pattern match out-of-order (match for mere presence); Just in the last 2 weeks, I have come across at least a couple instances when I was unable to add small unit tests to the testsuite because of this deficiency in FileCheck. Also, I agree with Krzysztof about the lack of any real recurring overhead. Can this feature please be added to