Displaying 6 results from an estimated 6 matches for "predicate_memop".
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
...ble converting some AVX patterns
over to the new system. I'm getting this error from tblgen:
VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
Here the tblgen pattern looks like this:
[(set VR256:$dst,...
2009 Jun 04
2
[LLVMdev] TableGen Type Inference
Can someone explain why TableGen can't figure this out?
VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32
(bitconvert:isInt (ld:v4i32 addr:iPTR:$src)<<P:Predicate_memop>>)))
llvm/tblgen: In VCVTDQ2PS128rm: Could not infer all types in pattern!
The pattern as written looks like this:
[(set VR128:$dst, (v4f32 (sint_to_fp (bc_memopv4i32 addr:$src))))]
I'm trying to unify AVX/SSE converts in a reasonable way. Right now,
X86InstrSSE.td doesn't have pa...
2010 Aug 05
0
[LLVMdev] x86 Vector Shuffle Patterns
...some AVX patterns
> over to the new system. I'm getting this error from tblgen:
>
> VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
> llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
It turns out this was a tblgen deficiency. I've got it fixed....
2009 Jun 05
0
[LLVMdev] TableGen Type Inference
...t's the node that didn't get
inferred.
Dan
On Jun 4, 2009, at 1:06 PM, David Greene wrote:
> Can someone explain why TableGen can't figure this out?
>
> VCVTDQ2PS128rm: (set:isVoid VR128:v4f32:$dst, (sint_to_fp:v4f32
> (bitconvert:isInt (ld:v4i32 addr:iPTR:$src)<<P:Predicate_memop>>)))
> llvm/tblgen: In VCVTDQ2PS128rm: Could not infer all types in pattern!
>
> The pattern as written looks like this:
>
> [(set VR128:$dst, (v4f32 (sint_to_fp (bc_memopv4i32 addr:$src))))]
>
> I'm trying to unify AVX/SSE converts in a reasonable way. Right now,
&g...
2009 Jun 17
0
[LLVMdev] help with tablegen
...e the SSE2 forms of ADD
are defined:
llvm[3]: Building X86.td DAG instruction selector implementation with tblgen
ADDPDrm: (set:isVoid VR128:isFP:$dst, (fadd:isFP
VR128:isFP:$src1, (ld:isFP
addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
/home/nicholas/llvm-commit/Debug/bin/tblgen: error:
Included from X86.td:128:
Included from X86InstrInfo.td:3964:
Parsing X86InstrSSE.td:1320: In ADDPDrm: Could not infer all types in
pattern!
defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd,
int_x86_sse2_add_sd, 1>;...
2010 Aug 05
1
[LLVMdev] x86 Vector Shuffle Patterns
...terns
>> over to the new system. I'm getting this error from tblgen:
>>
>> VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
>> llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
>
> It turns out this was a tblgen deficiency. I've go...