Displaying 10 results from an estimated 10 matches for "pred_sel_off".
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...vreg0<def> = COPY %T1_W; R600_TReg32:%vreg0
RESERVE_REG 0
%vreg4<def> = FNEG_R600 %vreg3; R600_Reg32:%vreg4 R600_TReg32:%vreg3
%vreg5<def> = MOV_IMM_F32 0.000000e+00; R600_Reg32:%vreg5
%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
%vreg7<def> = FNEG_R600 %vreg2; R600_Reg32:%vreg7 R600_TReg32:%vreg2
%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
%vreg10<def> = IMPLICIT_DEF; R600_Re...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...kill>; R600_Reg32:%vreg5,%vreg47
> 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
> 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
> 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
> 560BJUMP <BB#3>, pred:%PREDICATE_BIT
> 576BJUMP <BB#2>, pred:%nore...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...OPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
// LOOP BODY
896B...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
%vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3
%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Suc...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t;kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28
> %vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
> %vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
> %vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> %vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> %vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> %vreg32<def> = COPY %vreg3<kill>; R600_Reg128:%vreg32,%vreg3
> %vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vr...
2014 Feb 25
2
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
...f -print-after-all, llc generates the following MC in both plain LLVM 3.4 and LLVM 3.4 with my patch applied right after the "Finalize machine instruction bundles" pass:
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
%T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def>
%T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0...
2014 Feb 25
4
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
..., llc generates the following MC in both plain LLVM 3.4 and LLVM 3.4 with my patch applied right after the "Finalize machine instruction bundles" pass:
>>
>> %T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
>> %T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def>
>> %T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...B,832r:0)
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT: [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
register: %vreg47 +[400r,448B:0) phi-join +[448B,4...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...t;def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
> R600_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT:
> [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> register: %vreg47 +[400r,...