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...ID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:32:32" target endian = little target pointersize = 32 target triple = "i686-pc-linux-gnu" implementation ; Functions: void %execute() { entry: br bool false, label %bb688, label %cond_true cond_true: ; preds = %entry ret void bb: ; preds = %bb688 switch int 0, label %bb684 [ int 33, label %bb412 int 35, label %bb604 int 37, label %bb531 int 38, label %bb418 int 42, label %bb495 int 43, label %bb467 int 45, label %cond_true484 int 47, label %bb510 int 48, label %bb408...

...rne_ instruction or the _ldreq_ instruction should be removed. The error seems to come from the IfConvertion MachinePass. Here's is what it looks like before and after. > #BEFORE IfConversion MachinePass > > BB#7: > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3<def> = A...

...datalayout = "e-p:32:32" > target endian = little > target pointersize = 32 > target triple = "i686-pc-linux-gnu" > > implementation ; Functions: > > void %execute() { > entry: > br bool false, label %bb688, label %cond_true > > cond_true: ; preds = %entry > ret void > > bb: ; preds = %bb688 > switch int 0, label %bb684 [ > int 33, label %bb412 > int 35, label %bb604 > int 37, label %bb531 > int 38, label %bb418 > int 42, label %bb495 > int 43, label %bb467 > int 45, label %cond_true4...

...>>target endian = little >>target pointersize = 32 >>target triple = "i686-pc-linux-gnu" >> >>implementation ; Functions: >> >>void %execute() { >>entry: >> br bool false, label %bb688, label %cond_true >> >>cond_true: ; preds = %entry >> ret void >> >>bb: ; preds = %bb688 >> switch int 0, label %bb684 [ >> int 33, label %bb412 >> int 35, label %bb604 >> int 37, label %bb531 >> int 38, label %bb418 >> int 42, label %bb495 >> int 43, label %bb467 &g...

...cost: 1 degree: 3 gamma: 0.04545455 coef.0: 0 epsilon: 0.1 Number of Support Vectors: 754 > svm.model <- svm(similarity ~., data = training, kernel = "polynomial", cost = 1, degree = 3, gamma = 0.04545455, coef.0 = 0, epsilon = 0.1) > pred=predict(svm.model, testing) > pred[pred > .5] = 1 > pred[pred <= .5] = 0 > table(testing$similarity, pred) pred 0 1 0 30 8 1 70 63 > obj = best.tune(svm, similarity ~., data = training, kernel = "linear") > summary(obj) LINEAR: Call: best.tune(svm...

...+ ;; \ + ld8 reg = [reg] + +#define MOV_FROM_ITIR(reg) \ + movl reg = XSI_ITIR; \ + ;; \ + ld8 reg = [reg] + +#define MOV_FROM_ISR(reg) \ + movl reg = XSI_ISR; \ + ;; \ + ld8 reg = [reg] + +#define MOV_FROM_IHA(reg) \ + movl reg = XSI_IHA; \ + ;; \ + ld8 reg = [reg] + +#define MOV_FROM_IPSR(pred, reg) \ +(pred) movl reg = XSI_IPSR; \ + ;; \ +(pred) ld8 reg = [reg] + +#define MOV_FROM_IIM(reg) \ + movl reg = XSI_IIM; \ + ;; \ + ld8 reg = [reg] + +#define MOV_FROM_IIP(reg) \ + movl reg = XSI_IIP; \ + ;; \ + ld8 reg = [reg] + +.macro __MOV_FROM_IVR reg, clob + .ifc "\reg", &...

...ot; (prev), [tmp] "=&r" (tmp) : [p] "r" (p), [val] "r" (val) : "memory"); } ------------------------ # *** IR Dump Before Post RA top-down list latency scheduler ***: BB#6: derived from LLVM BB %if.else Live Ins: %LR %R2 %R3 %R4 %R7 %R12 Predecessors according to CFG: BB#0 CMPri %R12, 1, pred:14, pred:%noreg, %CPSR<imp-def> <<<<<<<<<<< First comparison using lock_flag ; R12 holds lock_flag %R5<def> = IMPLICIT_DEF Bcc <BB#21>, pred:1, pred:%CPSR<kill> <&l...

...ch as possible. For example, the header BB of a loop is transformed as follows (note that information in LiveVariables is not updated, so there may exist inconsistencies): BB2: preheader, BB3: header & latch, BB4: exit (before transformation) BB#2: derived from LLVM BB %entry.bb_crit_edge Predecessors according to CFG: BB#0 %reg1025<def> = MOVr %reg1034<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1024<def> = MOVr %reg1033<kill>, pred:14, pred:%reg0, opt:%reg0 %reg1036<def> = MOVi 0, pred:14, pred:%reg0, opt:%reg0 %reg1038<def...

...s, I use the part of the fit where the lower confidence interval is above zero as my criterion for positive association between the environmental variable and species abundance. However I like to plot this on the original scale of species abundance. To do so I extract the fit and SE using predict.gam. Lately I compared more carefully the plots I obtain in this way and those obtained with plot.gam and noticed differences which I do not understand. To avoid sending a large dataset I took an example from gam Help to illustrate this. Was I wrong to believe that the fit and its confi...

I'm trying to use Rprof() to identify bottlenecks and speed up a particullary slow section of code which reads in a portion of a tif file and compares each of the values to values of predictors used for model fitting. I've written up an example that anyone can run. Generally temp would be a section of a tif read into a data.frame and used later for other processing. The first portion which just records the time works in about 6 seconds the second part causes RGui to immediate...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14, pred:%reg0; mem:LD4[%uglygep2021] (after optimization) %reg1054<def>, %reg1033<def> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0 Are there any reasons they need to be removed? Would it br...

HI, Dear R community, I am writing the following function to create one data set(*tree.pred*) and one vector(*valid.out*) from loops. Later, I want to use the data set from this loop to plot curves. I have tried return, list, but I can not use the *tree.pred* data and *valid.out* vector. auc.tree<- function(msplit,mbucket) { * tree.pred<-data.frame() valid.out<-...

I am trying to load binary files in the following fashion load("pred/Pred_pres_a_indpdt") load("pred/Pred_pres_b_indpdt") load("pred/Pred_pres_c_indpdt") load("pred/Pred_pres_d_indpdt") load("pred/Pred_pres_e_indpdt") load("pred/Pred_pres_f_indpdt") but I would like to set up a for loop to replace the letters a...

...%reg16387<def> = COPY %R3<kill> 12L %reg16386<def> = COPY %R2<kill> 28L %reg16384<def> = COPY %R0<kill> 36L %reg16388<def> = COPY %reg16385<kill> 44L %reg16388<def>, %CPSR<def,dead> = tEOR %reg16388, %reg16387<kill>, pred:14, pred:%reg0 56L %reg16389<def> = COPY %reg16384<kill> 64L %reg16389<def>, %CPSR<def,dead> = tEOR %reg16389, %reg16386<kill>, pred:14, pred:%reg0 76L %reg16390<def>, %CPSR<def,dead> = tMOVi8 18, pred:14, pred:%reg0 88L %reg16391<def>...

...@some_func() noreturn After running it through "opt -loop-unswitch -S", it unswitched loop on %cond and produced result like this: define i32 @test(i1 %cond) { br i1 %cond, label %..split_crit_edge, label %.loop_exit.split_crit_edge .loop_exit.split_crit_edge: ; preds = %0 br label %loop_exit.split ..split_crit_edge: ; preds = %0 br label %.split .split: ; preds = %..split_crit_edge br label %loop_begin loop_begin: ; preds = %do_something, %.s...

...g to figure out why the restriction of LeaMI->getOperand(0).getReg() != BaseReg is there. It seems this is overly restrictive. For example, here is a case where it succeeds: 8944B BB#53: derived from LLVM BB %172 Live Ins: %R4 %R6 %D8 %Q5 %R9 %R7 %R8 %R10 %R5 %R11 Predecessors according to CFG: BB#52 8976B %R1<def> = t2LEApcrelJT <jt#2>, 2, pred:14, pred:%noreg 8992B %R1<def> = t2ADDrs %R1<kill>, %R10, 18, pred:14, pred:%noreg, opt:%noreg 9004B %LR<def> = t2MOVi 1, pred:14, pred:%noreg, opt:%noreg 90...

On Sat, Sep 4, 2010 at 1:31 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Sep 4, 2010, at 11:21 AM, Borja Ferrer wrote: > >> I've noticed this pattern happening with other operators aswell, but used xor in this example. As i said before, i tried with different register allocation orders, but it will produce always the same result. GCC is emitting longer

Here's what I've got so far - it seems to work, aside from the fact that DeleteDeadPHIs is not removing at least one dead PHI in my test program. --------------------- static bool mergeBlockIntoSuccessor(BasicBlock *pred, BasicBlock *succ) { if (succ == pred) return false; if (pred->getFirstNonPHI() != pred->getTerminator()) return false; // Delete the terminator in the predecessor block pred->getTerminator()->eraseFromParent(); // Update predecessor PHIs...

...r the *ldreq* instruction should be removed. The error seems > to come from the IfConvertion MachinePass. Here's is what it looks like > before and after. > > #BEFORE IfConversion MachinePass > > BB#7: > Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12 > Predecessors according to CFG: BB#5 BB#6 > STRBi12 %R5, %R6<kill>, 0, pred:14, pred:%noreg; > mem:ST1[%cond.i23.i.i.i] > %R6<def> = LDRBi12 %R7, 0, pred:14, pred:%noreg; mem:LD1[%15](align=4) > %R3<def> = EORri %R6, 254, pred:14, pred:%noreg, opt:%noreg > %R3...

...able > } > > declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind > > define fastcc void @c974001__lengthy_calculation. > 1736(%struct.FRAME.c974001* nocapture %CHAIN.185) noreturn { > entry: > br label %bb > > bb: ; preds = %bb, > %entry > br label %bb > } > > define fastcc void > @c974001__timed_calculation__calculation__B19b__B21b__A17b___clean. > 1830(%struct.FRAME.c974001__timed_calculation__calculationA* %CHAIN. > 188) { > entry: > ret void > } > > define fastcc v...