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...It would be better yes, though I'm not sure how you'd go about making that happen. It's probably not > worth worrying too much about though, as the new behaviour is still better than the old. OK, thanks for the clarification. I will reg-test and submit an updated patch soon. Thanks, Prathamesh > > John > > ________________________________ > From: Prathamesh Kulkarni <prathamesh.kulkarni at linaro.org> > Sent: 15 April 2020 01:44 > To: John Brawn <John.Brawn at arm.com> > Cc: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> > Subject: Re...

...by foldMemoryOperandImpl has mayLoad or mayLoadOrStore property set, and then proceed with adding memory operands, which seems to resolve the issue. Testing with make check-llvm with enable expensive checks doesn't show unexpected failures. Do the changes to foldMemoryOperand look OK ? Thanks, Prathamesh On Wed, 9 Sep 2020 at 22:30, Quentin Colombet <qcolombet at apple.com> wrote: > > Hi Prathamesh, > > What is the machine verifier error that you get? > > I am wondering if the issue is not in the machine verifier itself in the sense that it is somewhat reasonable to have ca...

On Tue, 16 Jun 2020 at 15:47, Tim Northover <t.p.northover at gmail.com> wrote: > > On Tue, 16 Jun 2020 at 10:23, Prathamesh Kulkarni via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > (b) Modifies RegisterCoalescer::reMaterializeTrivialDef and > > TargetInstrInfo::isReallyTriviallyReMaterializableGeneric to check > > for single live def, instead of single def. > > This seems dodgy to...

...to modify existing code, but not sure if it's a good idea ? (c) Make foldMemoryOperandImpl itself add memory operands, which will require somewhat more complicated changes in targets that already implement foldMemoryOperandImpl. I would be grateful for suggestions on how to proceed. Thanks, Prathamesh

...so, I guess, it only converted two calls to bl because further spilling wasn't necessary. However for above case, IIUC, we would want all calls to be converted to bl ? Since, 4 bl == 16 bytes 2 bl + 2 blx + 1 lr == 2 * 4 (bl) + 2 * 2 (blx) + 1 * 2 (ldr) + 4 bytes (litpool) == 18 bytes Thanks, Prathamesh On Fri, 10 Apr 2020 at 04:22, Prathamesh Kulkarni <prathamesh.kulkarni at linaro.org> wrote: > > Hi John, > Thanks for the suggestions! I will start looking at adding > foldMemoryOperand to ARMInstrInfo. > > Thanks, > Prathamesh > > On Tue, 7 Apr 2020 at 23:55,...

...pop {r0} bx r0 However I am not sure if the patch causes correctness issues. Testing with make check-llvm showed a relatively larger fallout (36 fail tests), which I am investigating. Just wanted to ask, is there something obviously wrong with the patch or the idea ? Thanks, Prathamesh -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-612-2.diff Type: application/octet-stream Size: 2132 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200616/dcda8ec1/attachment.obj>

...nk we could make use of that to do this. It looks like it would involve adding a foldMemoryOperand function to ARMInstrInfo and then have this fold a LDR into a BX by turning it into a BL. John ________________________________ From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Prathamesh Kulkarni via llvm-dev <llvm-dev at lists.llvm.org> Sent: 07 April 2020 21:07 To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] [ARM] Register pressure with -mthumb forces register reload before each call On Tue, 31 Mar 2020 at 22:03, Prathamesh Kulkarn...

...indirect call only when we know beforehand that it will not result in spilling. But I am not sure if it's possible to estimate that during isel ? I would be grateful for suggestions on how to proceed further. [1] https://github.com/intel/tinycrypt/blob/master/lib/source/ecc_dh.c#L139 Thanks, Prathamesh -------------- next part -------------- PreferIndirect: 1 PreferIndirect: 1 PreferIndirect: 1 Computing live-in reg-units in ABI blocks. 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 1...