Displaying 3 results from an estimated 3 matches for "pr_pp".
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_ADD]>;
> def :ItinRW<[2_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>;
>
> where n_LATENCY_WITH_p is defined roughly as:
>
> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> {
> let Latency = latency;
> let ResourceDelays = [latency];
> }
>
> class PR_Pp<int portIdx> : ProcResource<1>;
>
> The latency for register write-back/port access is static and without interlock, which I think means the port resources should have '...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...[II_ADD]>;
>>> def :ItinRW<[2_LATENCY_WITH_P0, 0_LATENCY_WITH_P1, 0_LATENCY_WITH_P2], [II_MUL]>;
>>>
>>> where n_LATENCY_WITH_p is defined roughly as:
>>>
>>> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> {
>>> let Latency = latency;
>>> let ResourceDelays = [latency];
>>> }
>>>
>>> class PR_Pp<int portIdx> : ProcResource<1>;
>>>
>>> The latency for register write-back/port access is static and without interlock,...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote:
> Hi Andy,
>
> I am trying to schedule and packetize instructions for VLIW at post-RA
> stage or final codegen stage, where code transformations are not allowed
> any more, because hardware can not resolve resource conflict. There is a
> simple example as following:
>
> ADD dest_reg1, src_reg1,