Displaying 7 results from an estimated 7 matches for "pr2916".
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pr24126
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
...n. Unfortunately I don't have
> > > the
> > > time to fix it. But please file a bug about this. Hopefully
> > > someone
> > > will fix it soon.
> > >
> > > Thanks,
> > >
> > > Evan
> > >
> >
> > PR2916 filed.
> > Though I did not quite understand why this could be a tablegen bug?
>
>
> Based on your comments. :-) It should be possible to specify two FSR0
> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> workaround you described:
>
>
> def...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:
>>>
>>> PR2916 filed.
>>> Though I did not quite understand why this could be a tablegen bug?
>>
>>
>> Based on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:...
2008 Oct 20
1
[LLVMdev] INSERT_SUBREG node.
On Mon, 2008-10-20 at 08:07 -0700, Evan Cheng wrote:
> On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:
>
> >>>
> >>> PR2916 filed.
> >>> Though I did not quite understand why this could be a tablegen bug?
> >>
> >>
> >> Based on your comments. :-) It should be possible to specify two FSR0
> >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> >&...
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...t; {
> > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > }
>
> This is a bug, probably in tablegen. Unfortunately I don't have the
> time to fix it. But please file a bug about this. Hopefully someone
> will fix it soon.
>
> Thanks,
>
> Evan
>
PR2916 filed.
Though I did not quite understand why this could be a tablegen bug?
- Sanjiv
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...SR8, FSR8]; // HERE.
>>> }
>>
>> This is a bug, probably in tablegen. Unfortunately I don't have the
>> time to fix it. But please file a bug about this. Hopefully someone
>> will fix it soon.
>>
>> Thanks,
>>
>> Evan
>>
>
> PR2916 filed.
> Though I did not quite understand why this could be a tablegen bug?
Based on your comments. :-) It should be possible to specify two FSR0
sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
workaround you described:
def FSR16: RegisterClass <"PIC16",...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote:
>>>
>>
>> Ok. The AX / AH super-reg and sub-reg relationship is not defined. In
>> general x86 is not making good use of the high 8-bit sub-registers.
>> We
>> are leaving some performance on the table. We'll probably fix it one
>> day. However, this doesn't apply to your target, right? There
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
On Wed, 2008-10-15 at 10:08 -0700, Evan Cheng wrote:
> On Oct 15, 2008, at 5:29 AM, sanjiv gupta wrote:
>
> > On Tue, 2008-10-14 at 10:19 -0700, Evan Cheng wrote:
> >> You need to specify sub-register == super-register, idx relationship.
> >> See X86RegisterInfo.td:
> >>
> >> def x86_subreg_8bit : PatLeaf<(i32 1)>;
> >> def