Displaying 4 results from an estimated 4 matches for "pr22603".
Did you mean:
22603
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
...lowering to
>> avoid this case. But I am using x86_64 target and it generates above
>> codes. How do you think about it? If I missed something, please let me
>> know.
JinGu,
Your analysis is correct, vectors of i1 are incorrectly legalized.
This is a known issue (http://llvm.org/PR22603); the tricky part about
fixing it is the need to settle on a memory layout for these vectors
(packed vs byte per i1; packed would be compatible with AVX512, I
think).
-Ahmed
>> Thanks,
>> JinGu Kang
> _______________________________________________
> LLVM Developers mailing lis...
2016 Jun 28
0
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
Can someone comment below question whether it is wrong or not please?
2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
> Hi All,
>
> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>
> Let's see a example.
>
> * LLVM IR
> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>
> * SelectionDAG before vector
2016 Jun 29
0
Question about VectorLegalizer::ExpandStore() with v4i1
...fcmp operation can be easily implemented using two instructions
to produce packed i1 values. Our software relies on this packed
representation extensively.
>
> JinGu,
>
> Your analysis is correct, vectors of i1 are incorrectly legalized.
> This is a known issue (http://llvm.org/PR22603); the tricky part about
> fixing it is the need to settle on a memory layout for these vectors
> (packed vs byte per i1; packed would be compatible with AVX512, I
> think).
>
> -Ahmed
>
2016 Jun 25
2
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
I have a problem with VectorLegalizer::ExpandStore() with v4i1.
Let's see a example.
* LLVM IR
store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
* SelectionDAG before vector legalization
ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
* SelectionDAG after vector legalization
ch = store<ST1[%16](align=4), trunc to i1> t0, t133, t32,