Displaying 3 results from an estimated 3 matches for "pr18303".
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pr13303
2014 Jan 14
2
[LLVMdev] 16-bit x86 status update
...heir operand size will take
their 32-bit form — a plain 'ret' will cause it to emit 'retl', etc.
We *could* support this mode, but it would be moderately non-trivial.
It would require the code emitter and the asm parser to maintain
separate ideas of the mode. The fix for PR18303 makes that somewhat
simpler, but still not entirely trivial. Alternatively we could add
yet another mode bit for the *parser*, but I don't like that much.
• GCC allows the compilation of C code to 16-bit mode by using
asm(".code16gcc") and also adding other flags such as...
2014 Jan 14
4
[LLVMdev] 16-bit x86 status update
...; their 32-bit form — a plain 'ret' will cause it to emit 'retl', etc.
> > We *could* support this mode, but it would be moderately non-trivial.
> > It would require the code emitter and the asm parser to maintain
> > separate ideas of the mode. The fix for PR18303 makes that somewhat
> > simpler, but still not entirely trivial. Alternatively we could add
> > yet another mode bit for the *parser*, but I don't like that much.
> >
> > • GCC allows the compilation of C code to 16-bit mode by using
> > asm(".code16gcc&...
2015 Feb 23
2
[LLVMdev] clang .code16 with -Os producing larger code that it needs to
On Fri, 2015-02-20 at 13:47 -0500, Rafael Espíndola wrote:
> > Your task, should you choose to accept it, is to make it cope with other
> > forms of relaxation where necessary.
>
> And if not, please open a bug :-)
http://llvm.org/bugs/show_bug.cgi?id=22662
FWIW I could reproduce the 'movl foo, %ebx' one but a relative jump
*was* using 16 bits (although gas uses 8):