Displaying 3 results from an estimated 3 matches for "pr17593".
2013 Oct 16
0
[LLVMdev] MI scheduler produce badly code with inline function
...com> wrote:
> Hi Andy, thanks for your help!!
> The scheduled code by method A is same as B when using the new machine model.
> it's make sense, but there is the another problem, the scheduled code is badly.
>
> load/store instruction always reuse the same register
I filed PR17593 with this information. However, I see opposite results from what you’re expecting. The code that uses fewer registers runs 4% faster on my cortex-a9. The integer unit is out-of-order.
> this is just because A9's per-operand machine model is not implemented well?
> By the way, why do you...
2013 Oct 16
3
[LLVMdev] MI scheduler produce badly code with inline function
Hi Andy, thanks for your help!!
The scheduled code by method A is same as B when using the new machine
model.
it's make sense, but there is the another problem, the scheduled code is
badly.
load/store instruction always reuse the same register
Source:
#define N 2000000
static double b[N], c[N];
void Scale () {
double scalar = 3.0;
for (int j=0;j<N;j++)
b[j] =
2013 Oct 21
1
[LLVMdev] MI scheduler produce badly code with inline function
...i Andy, thanks for your help!!
> The scheduled code by method A is same as B when using the new machine
> model.
> it's make sense, but there is the another problem, the scheduled code is
> badly.
>
> load/store instruction always reuse the same register
>
>
> I filed PR17593 with this information. However, I see opposite results
> from what you’re expecting. The code that uses fewer registers runs 4%
> faster on my cortex-a9. The integer unit is out-of-order.
>
> this is just because A9's per-operand machine model is not implemented
> well?
> By t...