Displaying 3 results from an estimated 3 matches for "pr16274".
2016 Feb 08
2
Vectorization with fast-math on irregular ISA sub-sets
Folks,
I'm now looking at https://llvm.org/bugs/show_bug.cgi?id=16274, which
seems to have some support in the vectorizer, but not as we need for
this particular case. I may have missed something obvious, please let
me know if there is a better way.
As you already know, ARM has two FP instruction sets: VFP and NEON.
VFP applies to single FP registers while NEON is a full SIMD. The
problem is
2013 Jun 07
1
[LLVMdev] NEON vector instructions and the fast math IR flags
On 7 June 2013 18:08, Arnold Schwaighofer <aschwaighofer at apple.com> wrote:
> What I am suggesting is that (if you care about denormals):
>
> * the arm backend has to be fixed to scalarize floating point vector
> operations (behind a flag)
> * the arm target transform model has to correctly reflect that
>
Yup. What I had in mind, too. This is why I asked Tobi to create
2016 Feb 08
3
Vectorization with fast-math on irregular ISA sub-sets
...6274 is probably a "won't fix"?
> My experience is that the number of people who care about pull IEEE compatibility on ARMv7 hardware is limited, and the set of people who care about exact ULP constraints even more limited. I think we absolutely should make a solution that solves PR16274, but I think it would have to be opt-in, not opt-out.
And I'm guessing this is related to SLP and others. If so, I agree.
So,
For 16275, the fix is to disable loop vect. for no-fast-math + hasUnsafeAlgebra.
For 16274, disabling NEON emission in SLP would be one way, but we
must avoid any fi...