Displaying 5 results from an estimated 5 matches for "pr1306".
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pr106
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
...>
> Is the work Evan doing a prerequisite for supporting vreg subregs?
Sort of. vreg subregs work can start before I finish phyregs subregs
support. But unless there are no live-in registers nothing can
possibly work.
> Is there a PR for the feature Evan is working on?
You filed it. PR1306. :-)
>
>>> Is any of this kind of work planned? The addition of those
>>> MRegisterInfo functions has me curious...
>>
>> This is on our mid-term plan, which means we'll probably tackle it
>> over
>> the next year or so, but we don't have any co...
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
Thanks for the detailed response.
On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote:
> Right. Evan is currently focusing on getting the late stages of
> the code
> generator (e.g. livevars) to be able to understand arbitrary machine
> instrs in the face of physreg subregs. This lays the groundwork for
> handling vreg subregs, but won't solve it directly.
Is the work Evan
2007 Apr 04
0
[LLVMdev] Live intervals and aliasing registers problem
On Apr 3, 2007, at 3:45 PM, Christopher Lamb wrote:
>
>> Can you dump out the machine basic block? It should have an
>> implicit use of V4R0 at first ORI but it should not be marked kill.
>> If it is marked kill, then you need to walk LiveVariables.cpp to
>> find out why.
>
> Here is the beginning of the BB dump.
>
> entry (0x8503c80, LLVM BB @0x8501af0,
2007 Apr 24
2
[LLVMdev] Register based vector insert/extract
...a prerequisite for supporting vreg subregs?
>
> Sort of. vreg subregs work can start before I finish phyregs subregs
> support. But unless there are no live-in registers nothing can
> possibly work.
>
>> Is there a PR for the feature Evan is working on?
>
> You filed it. PR1306. :-)
Ah! I didn't realize that the issue would have such far reaching
consequences.
>>>> Is any of this kind of work planned? The addition of those
>>>> MRegisterInfo functions has me curious...
>>>
>>> This is on our mid-term plan, which means we...
2007 Apr 03
2
[LLVMdev] Live intervals and aliasing registers problem
On Mar 27, 2007, at 3:25 PM, Evan Cheng wrote:
>
> On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote:
>
>> While beginning to add vector registers to a back end I came
>> across the following problem: as soon as I define two sets of
>> registers that have a many-to-one mapping the live interval pass
>> appears to double-kill the mapped-onto register. I