search for: ppwr

...iff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c index bcdc00f..060bbd2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c @@ -63,7 +63,6 @@ nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx) nv_wr32(ppwr, 0x10a580, 0x00000003); } while (nv_rd32(ppwr, 0x10a580) != 0x00000003); nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base); - nv_wr32(ppwr, 0x10a1c4, 0x00010000 | MEMX_ENTER); return 0; } @@ -79,7 +78,6 @@ nouveau_memx_fini(struct nouveau_mem...

Patch 1 and 2 implement wait-for-vblank, required to remove flicker when reclocking memory Patch 3 and 4 allow me to do things between waiting for VBLANK and disabling FB, like pause PFIFO and wait for the engines to idle. This minimises the time PFIFO is paused, thus maximises performance. The rest of the patches speak for themselves. As the actual memory reclocking script is still somewhat prone

...dev/pwr/base.c b/nvkm/subdev/pwr/base.c > index 0ab55f27ec45..1ea433a5e118 100644 > --- a/nvkm/subdev/pwr/base.c > +++ b/nvkm/subdev/pwr/base.c > @@ -26,7 +26,7 @@ > > #include "priv.h" > > -static void > +void > nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) > { > const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); > diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h > index 3814a341db32..86149d9a440c 100644 > --- a/nvkm/subdev/pwr/priv.h > +++ b/nvkm/subdev/pwr/priv.h > @@ -26,6 +26,7 @@ int _n...

There might be some callers of nouveau_clock_astate(), and they are from inetrrupt context. So we must ensure that this function can be atomic in that condition. This patch adds one parameter which is subsequently passed to nouveau_pstate_calc(). Therefore we can choose whether we want to wait for the pstate work's completion or not. Signed-off-by: Vince Hsu <vinceh at nvidia.com> ---

...core/subdev/fb/ramfuc.h @@ -141,6 +141,20 @@ ramfuc_wait_vblank(struct ramfuc *ram) } static inline void +ramfuc_train(struct ramfuc *ram) +{ + nouveau_memx_train(ram->memx); +} + +static inline int +ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize) +{ + struct nouveau_pwr *ppwr = nouveau_pwr(pfb); + + return nouveau_memx_train_result(ppwr, result, rsize); +} + +static inline void ramfuc_block(struct ramfuc *ram) { nouveau_memx_block(ram->memx); @@ -162,6 +176,8 @@ ramfuc_unblock(struct ramfuc *ram) #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (...

...ertions(+), 1 deletion(-) diff --git a/nvkm/engine/graph/nve4.c b/nvkm/engine/graph/nve4.c index 1ba6666da4e5..fb9cb929320d 100644 --- a/nvkm/engine/graph/nve4.c +++ b/nvkm/engine/graph/nve4.c @@ -203,7 +203,8 @@ nve4_graph_init(struct nouveau_object *object) int gpc, tpc, rop; int ret, i; - ppwr->pgob(ppwr, false); + if (ppwr) + ppwr->pgob(ppwr, false); ret = nouveau_graph_init(&priv->base); if (ret) -- 2.0.1

...2 insertions(+), 1 deletion(-) diff --git a/nvkm/subdev/pwr/base.c b/nvkm/subdev/pwr/base.c index 0ab55f27ec45..1ea433a5e118 100644 --- a/nvkm/subdev/pwr/base.c +++ b/nvkm/subdev/pwr/base.c @@ -26,7 +26,7 @@ #include "priv.h" -static void +void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) { const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h index 3814a341db32..86149d9a440c 100644 --- a/nvkm/subdev/pwr/priv.h +++ b/nvkm/subdev/pwr/priv.h @@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object...

...m/subdev/pwr/base.c >> index 0ab55f27ec45..1ea433a5e118 100644 >> --- a/nvkm/subdev/pwr/base.c >> +++ b/nvkm/subdev/pwr/base.c >> @@ -26,7 +26,7 @@ >> #include "priv.h" >> -static void >> +void >> nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) >> { >> const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); >> diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h >> index 3814a341db32..86149d9a440c 100644 >> --- a/nvkm/subdev/pwr/priv.h >> +++ b/nvkm/subdev/pwr/priv.h...

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

This patch fixes the pwr firmware to play nicely at least on NVA3. Because Martin might send more patches soon, I didn't include a regenerated nvXX.fuc.h. To me it makes more sense if all patches are merged then, and a final patch regenerates the headers in one go. Of course, I did test this patch and found it to work as intended, so feel free to pick up as you please.

...77aef65cae2c0becc3f5d560 # bad: [21136946c495b0e1e0f7e25a8de6f170efbdeadf] drm/vmwgfx: fix warning if config intel iommu is off. git bisect bad 21136946c495b0e1e0f7e25a8de6f170efbdeadf # good: [09b8d73bd5aa4a4897d2fa603e683f09ac7e9916] drm/nvc0/therm: allow fan control if we've killed the vbios ppwr ucode git bisect good 09b8d73bd5aa4a4897d2fa603e683f09ac7e9916 # good: [0833428e7d1b250afbd41e0a4c8c247cccd15aad] drm/nouveau/bios: parsing for various tables required for power management git bisect good 0833428e7d1b250afbd41e0a4c8c247cccd15aad # bad: [26fdd78cce3f51a49e1f2d3ad27ee893a28d220e] drm...

Re-use the therm-exported fan structure with only two minor modifications: - pwm_freq: u16 -> u32; - add fan_type (toggle or PWM) v2: - Do not memset the table to 0 as it erases the pre-set default values Signed-off-by: Martin Peres <martin.peres at free.fr> --- drm/Kbuild | 1 + drm/core/include/subdev/bios/fan.h | 1 + drm/core/subdev/bios/fan.c | 1