search for: ppctargetmachin

...arget/X86/X86CodeEmitter.cpp * Parameterized to support JITCodeEmitter and in future ObjectCodeEmitter lib/Target/X86/X86JITInfo.h lib/Target/X86/X86JITInfo.cpp * Replaced references to MachineCodeEmitter with JITCodeEmitter. lib/Target/PowerPC/PPC.h lib/Target/PowerPC/PPCTargetMachine.h lib/Target/PowerPC/PPCTargetMachine.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp * Parameterized to support JITCodeEmitter and in future ObjectCodeEmitter lib/Target/PowerPC/PPCJITInfo.h lib/Target/PowerPC/PPCJITInfo.cpp * Replaced references to MachineCodeEmitter with...

I'm having some troubles building LLVM 3.3 (previously I was using 3.2). I'm getting a lot of errors in the various architecture support: In file included from PPCFrameLowering.h:17:0, from PPCTargetMachine.h:17, from PPCSelectionDAGInfo.cpp:15: PPCSubtarget.h:60:49: error: expected class-name before ‘{’ token PPCSubtarget.h:196:30: error: ‘RegClassVector’ has not been declared In file included from AArch64Subtarget.cpp:14:0: AArch64Subtarget.h:29:57: error: expected class-name befo...

Hi, I am able to remove the critical edges now. I only had to insert the line below in PPCTargetmachine.cpp. PM.add(createBreakCriticalEdgesPass()); However, it does not remove all the critical edges. I am getting a very weird dataflow graph (even without the Break Critical edges pass). The dataflow generated by MachineFunction::dump() for the program below is given here: http://compilers.cs.ucl...

Dear guys, I've adapted the pass in BreakCriticalEdges.cpp so I can use it before register allocation. But the pass is not changing the control flow graph of the machine function. I think it is because I am inserting the pass after the control flow graph of the machine function is built. I am inserting the pass as required by the register allocator, and I can see that the pass is

...don't think "getValue(I.getArgOperand(1))" should be there. > return 0; > } > case Intrinsic::gcroot: > --- a/lib/Target/PowerPC/PPCISelLowering.cpp > +++ b/lib/Target/PowerPC/PPCISelLowering.cpp > @@ -211,6 +211,8 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) > setOperationAction(ISD::TRAP, MVT::Other, Legal); > > // TRAMPOLINE is custom lowered. > + setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); > + setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); > > // VASTART needs to be custom...

Hi! Attached set of patches splits llvm.init.trampoline into an "init" phase and an "adjust" phase, as discussed on the "Go on dragonegg" thread. Thanks! -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Split-intrinsics-and-DAG-nodes.patch Type: text/x-diff Size: 8808 bytes Desc:

....cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@ cl::Hidden); PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {...

...nately changing how code generator passes are added to pass managers require that we potentially make changes on target specific parts of the backend. Examples: file "Target/X86/X86TargetMachine.cpp"; file "Target/Sparc/SparcTargetMachine.cpp"; file "Target/PowerPC/PPCTargetMachine.cpp" etc. In general, changes are required in every place in the backend where decisions are made based on the optimization level. More specifically, changes are required in the following components: 1. Instruction Selector: -- Use the effective optimization level to decide whether F...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

....cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 53464) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@ cl::Hidden); PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

....cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@ cl::Hidden); PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

....cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@ cl::Hidden); PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) - : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()), - PPCAtomicLabelIndex(0) { + : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { setPow2DivIsCheap(); @@ -378,45 +377,47 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {...