search for: ppcstcx

...", + [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>; + } +} -let Defs = [CR0] in { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd :...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...", + [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>; + } +} -let Defs = [CR0] in { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd :...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...", + [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>; + } +} -let Defs = [CR0] in { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd :...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...", + [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>; + } +} -let Defs = [CR0] in { -def STDCX : Pseudo<(outs), (ins G8RC:$rS, memrr:$dst, i32imm:$label), - "stdcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", - [(PPCstcx G8RC:$rS, xoaddr:$dst, imm:$label)]>; +// Instructions to support atomic operations +def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), + "ldarx $rD, $ptr", LdStLDARX, + [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; -def CMP_UNRESd :...

...(CMP_UNRESw and STWCX) require multiple > instructions: > > let Defs = [CR0] in { > def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), > "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", > [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label), > "cmpw $rA, $rB\n\tbne- La${label}_exit", > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:$label)]>;...

...h attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label), "cmpw $rA, $rB\n\tbne- La${label}_exit", [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:$label)]>; } ...and I can...