search for: ppcregisterinfo

...Is there a simple way to just change the opcode of a machine > instruction. > > I have a lot of long/short pairs where when I know the offset, i can > replace the long version with the short version. Are you looking for something like this: MI.setDesc(TII.get(NewOpcode)); This is in PPCRegisterInfo::eliminateFrameIndex. -Hal > > Tia. > > REed > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >

To fix some problems with how condition registers are saved/restored for PowerPC, I need to override TargetRegisterInfo::hasReservedSpillSlot() in PPCRegisterInfo. I've had some difficulties because of the constness of the function, and I'm wondering what the best way to handle this would be. Essentially I need to add a field to PPCRegisterInfo, and modify that field in hasReservedSpillSlot. (I need to reserve the spill slot only if condition regi...

Is there a simple way to just change the opcode of a machine instruction. I have a lot of long/short pairs where when I know the offset, i can replace the long version with the short version. Tia. REed

...ill break. I can address this issue by using two tricks together: 1. Calling MachineFrameInfo::setHasCalls in my backend 2. Using the attached patch, so that value of setHasCalls is not reset to false later. Comments? BTW, I've checked other uses of MachineFrameInfo::hasCalls. For example, PPCRegisterInfo uses it to check if if callee save registers can be stored in something called "red zone", whatever that is. I wonder how this relates to interrupts. Say, function X is running. Interrupt arrives, and the interrupt handlers calls function X again. So, if that "red zone" is some...

I think the easiest thing for you to do is to define a separate CALL instruction with a different set of Defs. This instruction should only be selected when the predicate isMacho is true. Also update PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list when subtarget->isMachoABI() is true. Evan On Feb 14, 2007, at 7:19 AM, Nicolas Geoffray wrote: > Hi Chris, > > Chris Lattner wrote: >>> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved >>> regi...

...Jakob at least seems interested in the for loop stuff. Am I reading you > correctly, Jakob? Having that feature would make a huge difference. I think the for loops have merit, but not the way you want to use them. Some target descriptions have many sequential definitions, for example PowerPC/PPCRegisterInfo.td: // Vector registers def V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>; def V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>; ... def V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>; def V31 : VR<31, "v31">, DwarfRegNum<[1...

Hi Chris, Chris Lattner wrote: >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this I tried to define Defs just

...lean up gratuitous redundancy in one dimension, like the ADD and SUB having the exact same variants. If it isn't overused, it even helps readability. We are missing a mechanism for eliminating gratuitous sequential redundancy, and a for loop for top-level defs would help with that. Please use PPCRegisterInfo.td as the primary use case for a for loop. /jakob

...I was forgetting to initialize the array that records the physical registers ever used (MachineFunction::UsedPhysRegs). This is a very minor thing, but I would suggest asserting that the vector has been initialized before it is used in functions such as runOnMachineFunction::X86FloatingPoint.cpp or PPCRegisterInfo::emitPrologue. Now I have another question. My register allocator is generating code like this: .text .align 16 .globl main main: subl $2, %esp fnstcw (%esp) movb $2, 1(%esp) fldcw (%esp) xorl %eax, %eax movl %eax, %eax <--...

Hi Tim, I wonder if you could help me with the following, even if just giving some pointers about where to look. I previously posted a similar question in the mailing list, but unfortunately I have not received a reply. This is the subject: I want to reduce the number of register spills to the stack that are created around storeRegToStackSlot and loadRegFromStackSlot In order to do so, I can

Evan Cheng <evan.cheng at apple.com> writes: > David, we cannot accept the 'multidef' keyword. Please revert it. Working on it now. > We appreciate you thinking ahead about MIC, but we are against the > massive refactoring and complicated abstraction scheme. We'll never > accept those patches. How about a less massive and complicated scheme? I think we can make

...ld/./lib/Target/Sparc/Disassembler/Release+Asserts/SparcDisassembler.o differ: byte 42480, line 184 ./lib/Target/PowerPC/Release+Asserts/PPCISelDAGToDAG.o ../../recurse2be/build/./lib/Target/PowerPC/Release+Asserts/PPCISelDAGToDAG.o differ: byte 135005, line 376 ./lib/Target/PowerPC/Release+Asserts/PPCRegisterInfo.o ../../recurse2be/build/./lib/Target/PowerPC/Release+Asserts/PPCRegisterInfo.o differ: byte 51221, line 39 ./lib/Target/PowerPC/AsmParser/Release+Asserts/PPCAsmParser.o ../../recurse2be/build/./lib/Target/PowerPC/AsmParser/Release+Asserts/PPCAsmParser.o differ: byte 115582, line 306 ./lib/Target/P...

Evan Cheng wrote: > I think the easiest thing for you to do is to define a separate CALL > instruction with a different set of Defs. This instruction should > only be selected when the predicate isMacho is true. Also update > PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list > when subtarget->isMachoABI() is true. > Alright, thx Evan, that's what I did. Here are the final patches I think can be committed. I tried to separate them into independent chunks, but I'm not sure how to do this in a goo...

Hi Jakob and David, The for-loop inside multiclass definition does not have to add extra abstraction layer. As in the pseudo codes that David wrote earlier (see below), it only condenses the repetitive 'def' statements inside the multiclass definition into a more compact and less copy-paste style form, instead of encapsulating them somewhere outside the multiclass definition. I believe

...e complicated. If you look for uses of 'getRegisterMask' in Target/*/*ISelLowering.cpp, you'll see what I mean. Regardless, the code ends up calling some method is the targets TargetRegisterInfo subclass. These methods generally look something like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask...

...e complicated. If you look for uses of 'getRegisterMask' in Target/*/*ISelLowering.cpp, you'll see what I mean. Regardless, the code ends up calling some method is the targets TargetRegisterInfo subclass. These methods generally look something like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask...

...If you look for uses of 'getRegisterMask' > in Target/*/*ISelLowering.cpp, you'll see what I mean. Regardless, the code > ends up calling some method is the targets TargetRegisterInfo subclass. > These methods generally look something like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > CSR_SVR464_Altivec_Reg...

...tRegisterInfo subclass. These methods generally > > > > > look > > > > > something like this: > > > > > > > > > > > > > > > const uint32_t * > > > > > > > > > > > > > > > PPCRegisterInfo::getCallPreservedMask(const MachineFunction > > > > > &MF, > > > > > > > > > > > > > > > CallingConv::ID CC) const { > > > > > > > > > > > > > > > const PPCSubtarget &Subtarget =...

...'getRegisterMask' >> in Target/*/*ISelLowering.cpp, you'll see what I mean. Regardless, the code >> ends up calling some method is the targets TargetRegisterInfo subclass. >> These methods generally look something like this: >> >> const uint32_t * >> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >> CallingConv::ID CC) const { >> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >> ... >> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >> CS...

On Fri, 23 Jun 2006, Fernando Magno Quintao Pereira wrote: > I am getting an error with my pass implementation, and I cannot figure > it out. Basically, I've implemented part of a register allocation > algorithm, but I am having problems to set the passes correctly. For > instance, for this program below, the following error message is > produced: It's hard to say