Displaying 20 results from an estimated 62 matches for "ppcisellowering".
2008 Aug 22
3
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
...imm:$ls),
> + (i32 imm:$sl),
> + (i32 imm:$ss),
> + (i32 imm:$device)),
> + (SYNC)>;
> +
> include "PPCInstrAltivec.td"
> include "PPCInstr64Bit.td"
> Index: lib/Target/PowerPC/PPCISelLowering.cpp
> ===================================================================
> --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985)
> +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy)
> @@ -78,9 +78,6 @@
> // from FP_ROUND: that rounds to nearest, this rounds to zero....
2009 Feb 24
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
...33b9679 in abort ()
#4 0x933ae3db in __assert_rtn ()
#5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at
ValueTypes.h:317
#6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24,
SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx
= 4294967295}) at PPCISelLowering.cpp:311\
5
#7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR
(this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) at
PPCISelLowering.cpp:3200
#8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation
(this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) a...
2008 Aug 19
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
...er (i8 imm:$ll),
+ (i8 imm:$ls),
+ (i8 imm:$sl),
+ (i8 imm:$ss),
+ (i8 imm:$device)),
+ (SYNC)>;
+
include "PPCInstrAltivec.td"
include "PPCInstr64Bit.td"
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985)
+++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy)
@@ -78,9 +78,6 @@
// from FP_ROUND: that rounds to nearest, this rounds to zero.
setOperationAction(IS...
2010 Dec 29
2
[LLVMdev] Building LLVM on Linux/PowerPC failed
...nd Engine, altivec supported GNU/Linux
$ gcc --version
gcc (Gentoo 4.3.2-r3 p1.6, pie-10.1.5) 4.3.2
-----------------------------------------------------------------------
And here is the compiling error,
-----------------------------------------------------------------------
llvm[3]: Compiling PPCISelLowering.cpp for Release build
/tmp/chenwj/llvm-2.8/lib/Target/PowerPC/PPCISelLowering.cpp: In member
function 'llvm::SDValue
llvm::PPCTargetLowering::LowerFormalArguments_SVR4(llvm::SDValue,
llvm::CallingConv::ID, bool, const
llvm::SmallVectorImpl<llvm::ISD::InputArg>&, llvm::DebugLoc,
llvm::...
2009 Feb 25
3
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
...x933ae3db in __assert_rtn ()
> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4)
> at ValueTypes.h:317
> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24,
> SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0,
> dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\
> 5
> #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR
> (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0)
> at PPCISelLowering.cpp:3200
> #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation
> (this=0x1803d58, Op={Node = 0x157a530,...
2008 Aug 21
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
...32 imm:$ll),
+ (i32 imm:$ls),
+ (i32 imm:$sl),
+ (i32 imm:$ss),
+ (i32 imm:$device)),
+ (SYNC)>;
+
include "PPCInstrAltivec.td"
include "PPCInstr64Bit.td"
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985)
+++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy)
@@ -78,9 +78,6 @@
// from FP_ROUND: that rounds to nearest, this rounds to zero.
setOperationAction(IS...
2009 Feb 25
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
..._assert_rtn ()
>> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at
>> ValueTypes.h:317
>> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy =
>> llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at
>> PPCISelLowering.cpp:311\
>> 5
>> #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR
>> (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) at
>> PPCISelLowering.cpp:3200
>> #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation (this=0x1803d58,
>> Op=...
2009 Feb 25
0
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
...#4 0x933ae3db in __assert_rtn ()
> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4) at
> ValueTypes.h:317
> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24, SimpleTy =
> llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0, dl={Idx = 4294967295}) at
> PPCISelLowering.cpp:311\
> 5
> #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR
> (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0) at
> PPCISelLowering.cpp:3200
> #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation (this=0x1803d58,
> Op={Node = 0x157a530, ResNo...
2008 Jul 25
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Hi all,
I want to implement llvm.memory.barrier on PowerPC. The
implementation would be the single instruction "sync", but
currently it's defined with:
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand)
in lib/Target/PowerPC/PPCISelLowering.cpp, which causes it
to be a noop. I replaced the "Expand" with "Legal" in the
hope I'd get an error message that'd point me to where I
need to start adding stuff, but I just got the cryptic:
Cannot yet select: 0x10fc0500: ch = MemBarrier 0x10fc0368, 0x10fc0698, 0x10...
2009 Mar 02
1
[LLVMdev] [llvm-commits] [llvm] r65296 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/CellSPU/ lib/Target/PowerPC/ lib/Target/X86/ test/CodeGen/X86/
...t_rtn ()
>> #5 0x0008bd8f in llvm::MVT::getVectorElementType (this=0xbfffdda4)
>> at ValueTypes.h:317
>> #6 0x002aed06 in BuildSplatI (Val=0, SplatSize=8, VT={{V = 24,
>> SimpleTy = llvm::MVT::v4i32, LLVMTy = 0x18}}, DAG=@0x16088a0,
>> dl={Idx = 4294967295}) at PPCISelLowering.cpp:311\
>> 5
>> #7 0x002afae4 in llvm::PPCTargetLowering::LowerBUILD_VECTOR
>> (this=0x1803d58, Op={Node = 0x157a530, ResNo = 0}, DAG=@0x16088a0)
>> at PPCISelLowering.cpp:3200
>> #8 0x002bb54f in llvm::PPCTargetLowering::LowerOperation
>> (this=0x1803d5...
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
> prepare a updated patch?
This should work, though I won't have access to my test box now until
next Thursday so no guarantees :)
Cheers,
Gary
--
http://gbenson.net/
-------------- next part --------------
Index: lib/Target/PowerPC/PPCISelLowering.h
=====================...
2008 Aug 22
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
...(i32 imm:$sl),
>> + (i32 imm:$ss),
>> + (i32 imm:$device)),
>> + (SYNC)>;
>> +
>> include "PPCInstrAltivec.td"
>> include "PPCInstr64Bit.td"
>> Index: lib/Target/PowerPC/PPCISelLowering.cpp
>> ===================================================================
>> --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985)
>> +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy)
>> @@ -78,9 +78,6 @@
>> // from FP_ROUND: that rounds to nearest, t...
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> Hi all,
>
> I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled
> my patch (attached) on the implementation in X86, but when I try and
> compile my test file (also attached) with llc I get the error "Cannot
> yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68,
> 0x10fa4be0,
2007 Jan 12
2
[LLVMdev] Inserting an assembly instruction in the calling sequence of the powerpc target
...#39;m running into problems with vararg calls.
Before a variadic method is called, an extra instruction must be
executed (which is creqv 6, 6, 6). This
instruction is not necessary in Darwin/ppc.
I looked into the PowerPC target implementation and the code generation uses
Dags (lib/Target/PowerPC/PPCISelLowering.cpp, LowerCALL).
I need some help on how to insert the creqv instruction in the calling
sequence.
After this is implemented, I will be able to send a patch for linux/ppc
support.
I also need to know what is your preference for a linux/ppc target
implementation? I can either
1) Use macros (#if...
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>...
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
This looks OK to check in, do you have write access?
On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
> Dale Johannesen wrote:
>> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
>>> I'm trying to implement llvm.memory.barrier on PowerPC. I've
>>> modelled my patch (attached) on the implementation in X86, but
>>> when I try and compile my test
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
--
http://gbenson.net/
-------------- next part --------------
Index: lib/Target/PowerPC/PPCISelLowering.h
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.h (revision 52957)
+++ lib/Target/PowerPC/PPCISelLowering.h (working copy)
@@ -152,6 +152,11 @@
/// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
MTFSF,
+...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Look for createVirtualRegister. These are examples in
PPCISelLowering.cpp.
Evan
On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
> Hi Evan,
>
> Evan Cheng wrote:
>> The patch looks great. But I do have one comment:
>>
>> +let usesCustomDAGSchedInserter = 1 in {
>> + let Uses = [CR0] in {
>> + let Uses = [R0] in
>> +...
2008 Jul 08
3
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> The patch looks great. But I do have one comment:
>
> +let usesCustomDAGSchedInserter = 1 in {
> + let Uses = [CR0] in {
> + let Uses = [R0] in
> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>
> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> expanded like this later:
>
> + BuildMI(BB,
2008 Jul 12
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Committed. Thanks!
Evan
On Jul 11, 2008, at 1:07 PM, Gary Benson wrote:
> Hi Evan,
>
> Evan Cheng wrote:
>> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
>> prepare a updated patch?
>
> This should work, though I won't have access to my test box now until
> next Thursday so no guarantees :)
>
> Cheers,
> Gary
>
> --
> http://gbenson.net/
> <ppc-atomics-
> take4.patch>_________________...