search for: ppcinstraltivec

...bably a rewrite based around what > AltiVec does: Canonicalize to byte ops, and write all the patterns once > rather than having to look for 6 different variants of the same pattern. Can you expand on this with an example? There seems to be an awful lot of shuffle patterns and predicates in PPCInstrAltivec.td. What do you mean by, "Canonicalize to byte ops?" Can you walk me through how that works with Altivec? Since I'm rewriting all of the SSE patterns to clean them up and incorporate AVX functionality anyway, a complete rewrite of shuffles is not additional work. :) Thanks....

Hello, David > Can you expand on this with an example?  There seems to be an awful lot of > shuffle patterns and predicates in PPCInstrAltivec.td.  What do you mean by, > "Canonicalize to byte ops?"  Can you walk me through how that works with > Altivec? The basic idea is quite simple - lower everything to vNi8 and write all the patterns using only these types. -- With best regards, Anton Korobeynikov Faculty of Mathemat...

On Thursday 17 December 2009 18:04, Anton Korobeynikov wrote: > Hello, David > > > Can you expand on this with an example?  There seems to be an awful lot > > of shuffle patterns and predicates in PPCInstrAltivec.td.  What do you > > mean by, "Canonicalize to byte ops?"  Can you walk me through how that > > works with Altivec? > > The basic idea is quite simple - lower everything to vNi8 and write > all the patterns using only these types. Yeah, I figured that out after think...

...+// Memory barriers > +def : Pat<(membarrier (i32 imm:$ll), > + (i32 imm:$ls), > + (i32 imm:$sl), > + (i32 imm:$ss), > + (i32 imm:$device)), > + (SYNC)>; > + > include "PPCInstrAltivec.td" > include "PPCInstr64Bit.td" > Index: lib/Target/PowerPC/PPCISelLowering.cpp > =================================================================== > --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985) > +++ lib/Target/PowerPC/PPCISelLowering.cpp (working c...

..., (FMRSD (LFSX xaddr:$src))>; +// Memory barriers +def : Pat<(membarrier (i8 imm:$ll), + (i8 imm:$ls), + (i8 imm:$sl), + (i8 imm:$ss), + (i8 imm:$device)), + (SYNC)>; + include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -78,9 +78,6 @@...

...(FMRSD (LFSX xaddr:$src))>; +// Memory barriers +def : Pat<(membarrier (i32 imm:$ll), + (i32 imm:$ls), + (i32 imm:$sl), + (i32 imm:$ss), + (i32 imm:$device)), + (SYNC)>; + include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -78,9 +78,6 @@...

On Dec 17, 2009, at 3:10 PM, David Greene wrote: > I'm working on debugging AVX shuffles and I ran into an interesting > problem. > > The current isSHUFPMask predicate in X86ISelLowering needs to be > generalized to operate on 128-bit or 256-bit masks. There are > probably lots of other things to change too (LowerVECTOR_SHUFFLE_4wide, > etc.) but I'll worry about

On Dec 17, 2009, at 4:12 PM, David Greene wrote: > On Thursday 17 December 2009 18:04, Anton Korobeynikov wrote: >> Hello, David >> >>> Can you expand on this with an example? There seems to be an awful lot >>> of shuffle patterns and predicates in PPCInstrAltivec.td. What do you >>> mean by, "Canonicalize to byte ops?" Can you walk me through how that >>> works with Altivec? >> >> The basic idea is quite simple - lower everything to vNi8 and write >> all the patterns using only these types. > > Yeah, I...

...def : Pat<(membarrier (i32 imm:$ll), >> + (i32 imm:$ls), >> + (i32 imm:$sl), >> + (i32 imm:$ss), >> + (i32 imm:$device)), >> + (SYNC)>; >> + >> include "PPCInstrAltivec.td" >> include "PPCInstr64Bit.td" >> Index: lib/Target/PowerPC/PPCISelLowering.cpp >> =================================================================== >> --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 54985) >> +++ lib/Target/PowerPC/PPCISelLowe...

On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > Hi all, > > I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled > my patch (attached) on the implementation in X86, but when I try and > compile my test file (also attached) with llc I get the error "Cannot > yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, > 0x10fa4be0,

I'm working on debugging AVX shuffles and I ran into an interesting problem. The current isSHUFPMask predicate in X86ISelLowering needs to be generalized to operate on 128-bit or 256-bit masks. There are probably lots of other things to change too (LowerVECTOR_SHUFFLE_4wide, etc.) but I'll worry about that later. The generalized rule is: 1. For the low 64 bits of the result vector, the

This looks OK to check in, do you have write access? On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: > Dale Johannesen wrote: >> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: >>> I'm trying to implement llvm.memory.barrier on PowerPC. I've >>> modelled my patch (attached) on the implementation in X86, but >>> when I try and compile my test

...32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 53464) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...32 Load Instructions. @@ -1327,9 +1354,5 @@ def : Pat<(extloadf32 xaddr:$src), (FMRSD (LFSX xaddr:$src))>; -// Atomic operations -def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label), - (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>; - include "PPCInstrAltivec.td" include "PPCInstr64Bit.td" Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.cpp (working copy) @@ -40,8 +40,7 @@...