Displaying 2 results from an estimated 2 matches for "ppcgenmccodeemitter".
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ppcgencodeemitter
2015 Jun 25
2
[LLVMdev] TableGen question
...gt; opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
: I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
bits<3> CR;
bits<14> BD;
How does the generator match each variable against an operand?
For the corresponding PPCGenMCCodeEmitter.inc for this the entry is
// op: BIBO
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
// op: CR
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
// op: BD
op = getCondBrEncoding(MI, 2, Fixups, STI);
How does the generator know that BIBO is...
2012 Nov 13
2
[LLVMdev] [PATCH] .gitignore: add rules for a clean worktree
...fo.inc
diff --git a/lib/Target/PowerPC/.gitignore b/lib/Target/PowerPC/.gitignore
new file mode 100644
index 0000000..77c439b
--- /dev/null
+++ b/lib/Target/PowerPC/.gitignore
@@ -0,0 +1,8 @@
+PPCGenAsmWriter.inc
+PPCGenCallingConv.inc
+PPCGenCodeEmitter.inc
+PPCGenDAGISel.inc
+PPCGenInstrInfo.inc
+PPCGenMCCodeEmitter.inc
+PPCGenRegisterInfo.inc
+PPCGenSubtargetInfo.inc
diff --git a/lib/Target/Sparc/.gitignore b/lib/Target/Sparc/.gitignore
new file mode 100644
index 0000000..3708810
--- /dev/null
+++ b/lib/Target/Sparc/.gitignore
@@ -0,0 +1,6 @@
+SparcGenAsmWriter.inc
+SparcGenCallingConv.inc
+SparcGenDAGISel.in...