search for: postra

Hi all, Thanks for your feed-backs :-) @Andrew: In fact, I've reused most of the postRA list scheduler code and the resource priority queue. Every time it needs to move forward, either because of a res hazard (HazardRec) or an invalid combination of instructions in the current packet (DFA), it closes the current bundle and advances to the next cycle. The non-interlocked nature of...

...Andy, Thank you for your offer to work together on implementing the your new scheduler on X86. I can start working on this right away. In case you were unaware, the new Silvermont micro-architecture is only out of order on the integer side. The SSE instructions are still in order, so the current postRA scheduler is very beneficial for code with lots of SSE instructions, such as the ISPC (http://ispc.github.io) (example programs. Hence I would be looking at re-implementing the schedulers for both Atom and Silvermont. In the meantime, I would appreciate it if the current PostRA scheduler could be...

...is necessary. Other approaches/ideas are > very welcome. > Do you have any plan for adding a more robust bundler into the current > infrastructure ? > > Ivan Hi Ivan, Your description sounds fine to me. I assume you are totally decoupled from what LLVM currently calls the "postRA" scheduling pass. Hopefully you don't need anything in PostRASchedulerList.cpp. Running your bundler as a preEmit pass is the cleanest approach. But if need be, we can support preRA bundling at the time the MachineScheduler currently runs (if enabled). TargetPassConfig allows you to subst...

...one->getCurrMOps() && tryLatency(TryCand, Cand, *Zone)) return; Is this an error in comment or code? The CurrMOps is 0 once per cycle, which means this is actually done once per cycle, in contrast to what the comment suggests. ... // Schedule aggressively for latency in PostRA mode. We don't check for // acyclic latency during PostRA, and highly out-of-order processors will // skip PostRA scheduling. if (!OtherResLimited) { if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) { Policy.ReduceLatency |= true; Why !OtherR...

...additional features - not only bundle handling utilities, but also support for liveness computation, several (key) code transformation passes etc. (see my recent post for conditional defs for instance). Does your back-end perform any substantial transformations to the code _after_ the second pass (postRA) scheduler and bundle formation/finalization? Does any of them might demand bundle decomposition? If so, I really wonder how do you plan to address that. We also have an MI based version of the current VLIW scheduler, that I am planning to bring up to date with the tip, and upstream ASAP. But it...

Hi, On 08/09/2012 10:03 PM, Sergei Larin wrote: > I also tried to mess with PostRA scheduler to achieve similar goals, only > to find out that all the additional dependencies after RA make it virtually > impossible to produce high quality schedule, and obviously it is too late at > that point to address reg pressure via scheduling techniques, so I have put > that proj...

...Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Pekka Jääskeläinen > Sent: Friday, August 10, 2012 2:28 AM > To: llvmdev at cs.uiuc.edu; ivanllopard at gmail.com > Subject: Re: [LLVMdev] [RFC] Bundling support in the PostRA Scheduler > > Hi, > > On 08/09/2012 10:03 PM, Sergei Larin wrote: > > I also tried to mess with PostRA scheduler to achieve similar > > goals, only to find out that all the additional dependencies after RA > > make it virtually impossible to produce high quality s...

Hi, I'm working on a custom top-down post RA scheduler which builds bundles at the same time for our VLIW processor. I've borrowed most of the implementation from the resource priority queue implemented for the existent VLIW scheduler but applied to the context of MI scheduling. Basically, instructions that are likely to be bundled must be scheduled first (i.e. get higher priority).

...#39;ve hacked on the code quite a bit, the interaction between the scheduler and target hooks is still not obvious to me from glancing at the code. FWIW, I'm hoping it can be cleaned up gradually, maybe for the next release. The preRA scheduler is bottom-up, for register pressure tracking. The postRA scheduler is top-down, for simpler hazard detection logic. On ARM, the preRA scheduler uses an unspecialized instance of ScoreboardHazardRecognizer. The machine-independent RecedeCycle() logic that operates on the scheduler itinerary is sufficient. The ARM postRA scheduler specializes the HazardR...

...t; > -Tom > >> >> Andy, >> >> Those are just my guesses, but the issue looks very similar to our first >> experience with sched DAG constructor. >> >> Sergei Tom, The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. To me, the definition of "isSchedulingBoundary" is "some...

Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler....

On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > Tom, > > I do not have your call stack, but packetizer calls > ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is > the first time you use the new MI sched infrastructure (like your target has > not implemented misched yet) there might be some work needed to implement > couple target

...r in the queue until the scheduler reached cycle [24]. So three additional stores would have been scheduled first. HasReadyFilter effectively treats operand latency stalls as strictly as pipeline hazards. It's not clear to me that want to do that though if you fix getSchedulingPreference and do postRA scheduling later anyway. So it should work to do "hybrid" scheduling biased toward ILP, vs. "ilp" scheduling which really does the opposite of what it's name implies because it's initially biased toward regpressure. -Andy >> >> In addition, the stall comp...

...o leave in the single, simple switch for a period of time for folks to disable it if need be. > > > I just added a flag: -misched-bench. You can use it to flip back and forth between your target's default SD scheduler and the machine scheduler. It's doesn't affect whether the postRA scheduler is also run. If there are still no objections, I’ll plan to switch the x86 default to MI scheduler on Monday. -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131004/95cbf76a/attachment.html...

...> >> > >> Those are just my guesses, but the issue looks very similar to our first > >> experience with sched DAG constructor. > >> > >> Sergei > > Tom, > > The version of VLIWPacketizerList currently checked in was designed to work for postRA scheduling. I want it to be adapted for use in preRA (called by MachineScheduler), but Sergei and others are still engaged in that process. Since nothing is checked in yet, you'll be running into the same issues as Sergei. Ok, so I think I'll do a postRA packetizer for now and them come ba...

...ment, I am quite happy with a simple bottom-up basic-block scheduler. I tried to use a combination of the DFAPacketizer and a simple delay-slot-filler pass first, but the results are quite bad, both in terms of performance and in terms of maintainability/code quality. I found that currently the PostRA scheduler is nearly similar to the MI Scheduler, except that it uses the Anti-Dep-Breaker instead of live register tracking and that it is not customizable, while the MI scheduler cannot be run post-RA due to the dependency on the live variable analysis which requires SSA code. We would like t...

...e really good to leave in the single, simple switch for a period of time for folks to disable it if need be. I just added a flag: -misched-bench. You can use it to flip back and forth between your target's default SD scheduler and the machine scheduler. It's doesn't affect whether the postRA scheduler is also run. -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130925/6dfcb500/attachment.html>

...ang needs a blurb describing what's new in 2.7. Have the clang folks been doing anything for the last 6 months? 2. I need a few-line description of: "New LSR with "full strength reduction" mode, ideally with a link to a blog post entry or something. 3. I need a description of: PostRA scheduler for X86? FIXME: is this on by default in 2.7? 4. I need a description for: The ARM and Thumb code generators now using register scavenging for stack object address materialization.(FIXME: WHAT BENEFIT DOES THIS PROVIDE?) Please feel free to commit directly to llvm/docs/ReleaseNotes.html...

...information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required until SD and PostRA schedulers are replaced by MachineScheduler. This poses several question as to: 1) which representation gives the better cost estimation? 2) AFAIK, MachineScheduler can also take advantage from InstrItineraries with the ScoreboardHazardRecognizer for better cost estimation and scheduling. What is...

> it should be expanded late: In lib/Target/X86/X86MCInstLower.cpp. This is exactly what I was missing. Thanks a ton! :) -- Sanjoy Das http://playingwithpointers.com