Displaying 6 results from an estimated 6 matches for "postencodermethod".
2011 Aug 30
2
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...bly others. (None of these problems appear to be fixed in the current svn head either as far as I can tell.)
1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
case ARM::VLDRD:
case ARM::VSTRD: {
// op: p
op = getMachineOpValue(MI, MI.getOperand(3));
Value |= (op & 15U) << 28;
// etc ...
Value = VFPThumb2PostEncoder(MI, Value); // <--- overwr...
2011 Aug 30
0
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...der is rapidly maturing is generally passable for static encoding, but the MCJIT is still in its infancy.
> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>
> case ARM::VLDRD:
> case ARM::VSTRD: {
> // op: p
> op = getMachineOpValue(MI, MI.getOperand(3));
> Value |= (op & 15U) << 28;
> // etc ...
> Value = VFPThumb2PostEncoder(MI,...
2011 Aug 30
2
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...nction until the MC encoder is sufficiently far along that this one can be eliminated entirely."
>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>
>>
>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>> should be
>> Case += " Value |...
2011 Aug 30
0
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...nction until the MC encoder is sufficiently far along that this one can be eliminated entirely."
>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>
>>
>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>> should be
>> Case += " V...
2012 Oct 15
2
[LLVMdev] Alternate instruction encoding for subtargets
Hello,
I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to
create a subtarget for the new cpu version called KCPSM6. Besides a
couple of new instructions which are not important at the moment, the
KCPSM6 cpu has different instruction opcodes. Semantically the
instructions are the same, hence I'd like to keep all the lowering and
pattern matching stuff unmodified
For
2011 Aug 30
5
[LLVMdev] ARMCodeEmitter.cpp JIT support very broken (2.9 and svn)
...til the MC encoder is sufficiently far along that this one can be eliminated entirely."
>
>>> 1) VFP/Neon instructions don't encode correctly at al, because the encoding methods generated by tablegen for them clobber the constructed binary value when they try to implement 'PostEncoderMethod' support , for example, from ARMGenCodeEmitter.inc:
>>>
>>>
>>> The bug here is that in utils/TableGen/CodeEmitterGen.cpp, line 196:
>>> Case += " Value = " + PostEmitter + "(MI, Value);\n";
>>> should be
>>>...