search for: post_ldriuh

...he copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> // Use the lo subreg that was setup in MI1: .......

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...check if we can merge the two ranges of B into a single range. > However, this is not safe if A3 is a subreg define while A3 is not a subreg > use. > For instance, consider this code (part of a single block loop). > > MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, > 2, // Post Inc. Load. Vreg7 is a 64bit reg. > MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> > // This is the A3 = B0 above. > MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> > // Use the lo subreg th...

...case Hexagon::POST_LDrih: >> + case Hexagon::POST_LDrih_cPt: >> + case Hexagon::POST_LDrih_cNotPt: >> + case Hexagon::POST_LDrih_cdnPt_V4: >> + case Hexagon::POST_LDrih_cdnNotPt_V4: >> + >> + // Load unsigned halfword >> + case Hexagon::POST_LDriuh: >> + case Hexagon::POST_LDriuh_cPt: >> + case Hexagon::POST_LDriuh_cNotPt: >> + case Hexagon::POST_LDriuh_cdnPt_V4: >> + case Hexagon::POST_LDriuh_cdnNotPt_V4: >> + >> + // Load word >> + case Hexagon::POST_LDriw: >> + case Hexag...