Displaying 20 results from an estimated 61 matches for "popfq".
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2020 Aug 07
2
[PATCH v3 4/7] x86/paravirt: remove 32-bit support from PARAVIRT_XXL
...shf; pop %[re]ax
> .mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax
> .mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax
> -# ifdef CONFIG_X86_64
> .mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3
> .irq_restore_fl = { 0x57, 0x9d }, // push %rdi; popfq
> .cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd
> @@ -50,19 +45,11 @@ static const struct patch_xxl patch_data_xxl = {
> 0x48, 0x0f, 0x07 }, // swapgs; sysretq
> .cpu_swapgs = { 0x0f, 0x01, 0xf8 }, // swapgs
> .mov64 = { 0x48, 0x89, 0xf8 }, // mov %rdi, %rax
> -# else...
2020 Aug 07
2
[PATCH v3 4/7] x86/paravirt: remove 32-bit support from PARAVIRT_XXL
...shf; pop %[re]ax
> .mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax
> .mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax
> -# ifdef CONFIG_X86_64
> .mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3
> .irq_restore_fl = { 0x57, 0x9d }, // push %rdi; popfq
> .cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd
> @@ -50,19 +45,11 @@ static const struct patch_xxl patch_data_xxl = {
> 0x48, 0x0f, 0x07 }, // swapgs; sysretq
> .cpu_swapgs = { 0x0f, 0x01, 0xf8 }, // swapgs
> .mov64 = { 0x48, 0x89, 0xf8 }, // mov %rdi, %rax
> -# else...
2016 Feb 29
2
X86 Backend - How to push and pop eflags?
...3133b0)
- instruction: PUSHF64- operand 2: %EFLAGS<imp-use,kill>
Anyway right now i'm able to push it via some "dirty" INLINE_ASM.
2) INLINE_ASM works pretty well, except in one randomly generated test case
where the register allocator spills a register in between the pushfq/popfq,
resulting in a crash of the compiled application.
So the question is: is there a recommended way to save and restore the
value of eflags?
Any help is really appreciated!
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2017 Feb 25
2
rL296252 Made large integer operation codegen significantly worse.
...state of affair in that area degraded quite
significantly, see test/CodeGen/X86/i256-add.ll for instance.
Is there some kind of work in progress here and it is expected to get
better ? Because if not, that's a big problem. It looks like the problem is
that the compiler now choose to use pushfq/popfq in some cases rather than
chaining adc to propagate the carry in additions.
I hope this can get sorted out quickly. I'm happy to help if that is
necessary.
Thanks,
Amaury SECHET
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2015 Jul 29
2
[LLVMdev] optimizer clobber EFLAGS
...# c <bar+0xc>
c: 9c pushfq
d: 5b pop %rbx
e: e8 00 00 00 00 callq 13 <bar+0x13>
13: b8 01 00 00 00 mov $0x1,%eax
18: 53 push %rbx
19: 9d popfq
1a: 75 07 jne 23 <bar+0x23>
1c: e8 00 00 00 00 callq 21 <bar+0x21>
21: 31 c0 xor %eax,%eax
23: 5b pop %rbx
24: c3 retq
---
The critical bits here are that at 0xc/0...
2011 Sep 30
2
[LLVMdev] LLVM backends instruction selection
I am new to the LLVM backends, I am wondering how instruction selection is
done in LLVM backends, I looked at the .td files in Target/X86, they all
seem to be small and do not deal with common X86 instructions, i.e. mov,
push, pop, etc.
Thanks
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2015 Jul 29
0
[LLVMdev] optimizer clobber EFLAGS
...t;
> c: 9c pushfq
> d: 5b pop %rbx
> e: e8 00 00 00 00 callq 13 <bar+0x13>
> 13: b8 01 00 00 00 mov $0x1,%eax
> 18: 53 push %rbx
> 19: 9d popfq
> 1a: 75 07 jne 23 <bar+0x23>
> 1c: e8 00 00 00 00 callq 21 <bar+0x21>
> 21: 31 c0 xor %eax,%eax
> 23: 5b pop %rbx
> 24: c3 retq
>
> ---
>
> Th...
2007 Apr 18
0
[PATCH] paravirt_ops x86_64 , take 2
...r modify
it under the terms of the GNU General Public License as published by
@@ -59,11 +59,14 @@ void memory_setup(void)
asm("start_" #name ": " code "; end_" #name ":")
DEF_NATIVE(cli, "cli");
DEF_NATIVE(sti, "sti");
-DEF_NATIVE(popfq, "pushq %rax; popfq");
+/* We push rdi , and pop in rda. This is due to x86_64 calling conventions
+ * Recall that we are patching a function call */
+DEF_NATIVE(popfq, "pushq %rdi; popfq");
DEF_NATIVE(pushfq, "pushfq; popq %rax");
DEF_NATIVE(pushfq_cli, "pushfq...
2007 Apr 18
0
[PATCH] paravirt_ops x86_64 , take 2
...r modify
it under the terms of the GNU General Public License as published by
@@ -59,11 +59,14 @@ void memory_setup(void)
asm("start_" #name ": " code "; end_" #name ":")
DEF_NATIVE(cli, "cli");
DEF_NATIVE(sti, "sti");
-DEF_NATIVE(popfq, "pushq %rax; popfq");
+/* We push rdi , and pop in rda. This is due to x86_64 calling conventions
+ * Recall that we are patching a function call */
+DEF_NATIVE(popfq, "pushq %rdi; popfq");
DEF_NATIVE(pushfq, "pushfq; popq %rax");
DEF_NATIVE(pushfq_cli, "pushfq...
2015 Jul 29
0
[LLVMdev] optimizer clobbering EFLAGS
...# c <bar+0xc>
c: 9c pushfq
d: 5b pop %rbx
e: e8 00 00 00 00 callq 13 <bar+0x13>
13: b8 01 00 00 00 mov $0x1,%eax
18: 53 push %rbx
19: 9d popfq
1a: 75 07 jne 23 <bar+0x23>
1c: e8 00 00 00 00 callq 21 <bar+0x21>
21: 31 c0 xor %eax,%eax
23: 5b pop %rbx
24: c3 retq
The critical bits here are that at 0xc/0xd, w...
2020 Jul 24
0
[PATCH v5 31/75] x86/head/64: Load GDT after switch to virtual addresses
...we're currently running on. We have to do that here
+ * because in 32bit we couldn't load a 64bit linear address.
+ */
+ lgdt early_gdt_descr(%rip)
+
/* Check if nx is implemented */
movl $0x80000001, %eax
cpuid
@@ -193,14 +201,6 @@ SYM_CODE_START(secondary_startup_64)
pushq $0
popfq
- /*
- * We must switch to a new descriptor in kernel space for the GDT
- * because soon the kernel won't have access anymore to the userspace
- * addresses where we're currently running on. We have to do that here
- * because in 32bit we couldn't load a 64bit linear address.
- *...
2020 Jul 24
0
[PATCH v5 32/75] x86/head/64: Load segment registers earlier
...init data section until
+ * the per cpu areas are set up.
+ */
+ movl $MSR_GS_BASE,%ecx
+ movl initial_gs(%rip),%eax
+ movl initial_gs+4(%rip),%edx
+ wrmsr
+
/* Check if nx is implemented */
movl $0x80000001, %eax
cpuid
@@ -201,32 +227,6 @@ SYM_CODE_START(secondary_startup_64)
pushq $0
popfq
- /* set up data segments */
- xorl %eax,%eax
- movl %eax,%ds
- movl %eax,%ss
- movl %eax,%es
-
- /*
- * We don't really need to load %fs or %gs, but load them anyway
- * to kill any stale realmode selectors. This allows execution
- * under VT hardware.
- */
- movl %eax,%fs
- movl %eax,%...
2020 Jul 24
0
[PATCH v5 33/75] x86/head/64: Switch to initial stack earlier
...rsp
+
/* Check if nx is implemented */
movl $0x80000001, %eax
cpuid
@@ -220,9 +226,6 @@ SYM_CODE_START(secondary_startup_64)
/* Make changes effective */
movq %rax, %cr0
- /* Setup a boot time stack */
- movq initial_stack(%rip), %rsp
-
/* zero EFLAGS after setting rsp */
pushq $0
popfq
--
2.27.0
2020 Aug 07
0
[PATCH v3 4/7] x86/paravirt: remove 32-bit support from PARAVIRT_XXL
...; .mmu_read_cr2 = { 0x0f, 0x20, 0xd0 }, // mov %cr2, %[re]ax
>> .mmu_read_cr3 = { 0x0f, 0x20, 0xd8 }, // mov %cr3, %[re]ax
>> -# ifdef CONFIG_X86_64
>> .mmu_write_cr3 = { 0x0f, 0x22, 0xdf }, // mov %rdi, %cr3
>> .irq_restore_fl = { 0x57, 0x9d }, // push %rdi; popfq
>> .cpu_wbinvd = { 0x0f, 0x09 }, // wbinvd
>> @@ -50,19 +45,11 @@ static const struct patch_xxl patch_data_xxl = {
>> 0x48, 0x0f, 0x07 }, // swapgs; sysretq
>> .cpu_swapgs = { 0x0f, 0x01, 0xf8 }, // swapgs
>> .mov64 = { 0x48, 0x89, 0xf8 }, // mov...
2017 Feb 28
2
rL296252 Made large integer operation codegen significantly worse.
...>> significantly, see test/CodeGen/X86/i256-add.ll for instance.
>>
>> Is there some kind of work in progress here and it is expected to get
>> better ? Because if not, that's a big problem. It looks like the problem is
>> that the compiler now choose to use pushfq/popfq in some cases rather than
>> chaining adc to propagate the carry in additions.
>>
>> I hope this can get sorted out quickly. I'm happy to help if that is
>> necessary.
>>
>> Thanks,
>>
>> Amaury SECHET
>>
>
>
> _____________________...
2017 Oct 25
0
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
...lude <asm/asm-offsets.h>
> +#include <asm/special_insns.h>
> #include <linux/stringify.h>
>
> -DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
> -DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
> -DEF_NATIVE(pv_irq_ops, restore_fl, "pushq %rdi; popfq");
> -DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax");
> -DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
> -DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
> -DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
> -DEF_NAT...
2015 Jul 30
2
[LLVMdev] optimizer clobber EFLAGS
...pushfq
>> d: 5b pop %rbx
>> e: e8 00 00 00 00 callq 13 <bar+0x13>
>> 13: b8 01 00 00 00 mov $0x1,%eax
>> 18: 53 push %rbx
>> 19: 9d popfq
>> 1a: 75 07 jne 23 <bar+0x23>
>> 1c: e8 00 00 00 00 callq 21 <bar+0x21>
>> 21: 31 c0 xor %eax,%eax
>> 23: 5b pop %rbx
>> 24: c3 retq
>&g...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 01/17] paravirt_ops - core changes
...+ asm("start_" #name ": " code "; end_" #name ":")
+DEF_NATIVE(cli, "cli");
+DEF_NATIVE(sti, "sti");
+/* We push rdi , and pop in rda. This is due to x86_64 calling conventions
+ * Recall that we are patching a function call */
+DEF_NATIVE(popfq, "pushq %rdi; popfq");
+DEF_NATIVE(pushfq, "pushfq; popq %rax");
+DEF_NATIVE(pushfq_cli, "pushfq; popq %rax; cli");
+DEF_NATIVE(iret, "iretq");
+DEF_NATIVE(sysretq, "sysretq");
+DEF_NATIVE(swapgs, "swapgs");
+
+static const struct native_i...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 01/17] paravirt_ops - core changes
...+ asm("start_" #name ": " code "; end_" #name ":")
+DEF_NATIVE(cli, "cli");
+DEF_NATIVE(sti, "sti");
+/* We push rdi , and pop in rda. This is due to x86_64 calling conventions
+ * Recall that we are patching a function call */
+DEF_NATIVE(popfq, "pushq %rdi; popfq");
+DEF_NATIVE(pushfq, "pushfq; popq %rax");
+DEF_NATIVE(pushfq_cli, "pushfq; popq %rax; cli");
+DEF_NATIVE(iret, "iretq");
+DEF_NATIVE(sysretq, "sysretq");
+DEF_NATIVE(swapgs, "swapgs");
+
+static const struct native_i...
2017 Oct 04
1
[PATCH 03/13] x86/paravirt: Convert native patch assembly code strings to macros
...e <asm/paravirt.h>
#include <asm/asm-offsets.h>
+#include <asm/special_insns.h>
#include <linux/stringify.h>
-DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
-DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
-DEF_NATIVE(pv_irq_ops, restore_fl, "pushq %rdi; popfq");
-DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax");
-DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
-DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
-DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
-DEF_NATIVE(pv_mmu_ops, flush_tlb...