search for: popcount

Displaying 20 results from an estimated 36 matches for "popcount".

2011 Mar 16
2
Numeric vector converted mysteriously to characters in data frame?
...9","10-14","15-19","20-24","25-29","30-34","35-39", "40-44","45-49","50-54","55-59","60-64","65-69","70-74","75-79","80-84","85 plus") popcount <- c(35274,40958,41574,47973,50384,51248,65748,54854,60948,66473,70854, 60475,61854,55848,45857,30584,25475,20574) region <- "North East" test1 <- as.data.frame(cbind(region,ageband,agenames,popcount)) region <- "North West" test2 <- as.data.frame(cbind(region,a...
2010 Jan 27
2
[LLVMdev] some llvm/clang missed optimizations
>> Repetitive code with lots of bitwise operations is compiled by LLVM into >> much larger code than the other compilers: >> >> http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/ED/ED37DAF5.shtml >> http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/1F/1F4003C7.shtml >> >> Note that this is straight-line code, so LLVM's output will
2010 Jan 27
0
[LLVMdev] some llvm/clang missed optimizations
...symmetry of >> the code that the test harness duplicated by reducing the masking >> constants.  Probably too complicated for too little gain to be worth >> pursuing. > > There are a bunch of these actually, I can try to make a list... Umm, can you find one that isn't a popcount implementation? -Eli
2010 Jan 27
2
[LLVMdev] some llvm/clang missed optimizations
> Umm, can you find one that isn't a popcount implementation? Ok. MMX psadbw instruction: http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/CE/CE3DA132.shtml Position of first set bit: http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/1F/1F4003C7.shtml Log2 floor: http://embed.cs.utah.edu/embarrassing/jan_10/harvest/...
2013 Aug 16
2
[LLVMdev] ctlz pattern
Does anyone know some simple c/c++ code or .ll code which will cause this ctlz pattern to be emitted? Tia. Reed
2013 Aug 16
0
[LLVMdev] ctlz pattern
Are you looking for something other than calling __builtin_clz from c++ or calling @llvm.ctlz.* instrinsic from IR? I don't think we have anything that will auto converting a loop to ctlz or anything like that. We only seem to have a detection for popcount loops. On Thu, Aug 15, 2013 at 9:01 PM, reed kotler <rkotler at mips.com> wrote: > Does anyone know some simple c/c++ code or .ll code which will cause this > ctlz pattern to be emitted? > > Tia. > > Reed > > > ______________________________**_________________ &g...
2008 Feb 20
1
[LLVMdev] ctpop intrinsic question
...lemented algorithm is essentially the first of the 3 given tree reduction based algorithms given in http://en.wikipedia.org/wiki/Hamming_weight?? How can I emit that intrinsic from LLVMBuilder? What is the correct LLVM textual IR representation? I tried ; ModuleID = 'test' define i64 @popcount(i64 %x) { entry: %tmp = call i64 @llvm.ctpop.i64(i64 %x) ret i64 %tmp } which gives me errors .. I tried several others and read the lang. ref., but I don't get it;( Any hints appreciated, Tobias
2018 Jun 02
2
LoopIdiomRecognize is not recognizing the ctpop idiom
...if (x & 1) numBits++; x >>= 1; } return numBits; } I also did check the following code, getting inspired from the discussion at http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20121119/156300.html: int popcount_Yang_i32(int a) { int c = 0; while (a) { c++; //... // both a & c would be used multiple times in or out of //loop a &= a - 1; //... } return c;...
2010 Jan 27
0
[LLVMdev] some llvm/clang missed optimizations
On Tue, Jan 26, 2010 at 7:42 PM, John Regehr <regehr at cs.utah.edu> wrote: >> Umm, can you find one that isn't a popcount implementation? > > Ok. > > MMX psadbw instruction: > > http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/CE/CE3DA132.shtml > > Position of first set bit: > > http://embed.cs.utah.edu/embarrassing/jan_10/harvest/source/1F/1F4003C7.shtml > > Log2 floor:...
2007 Jul 30
1
[LLVMdev] For the avoidance of doubt...
Chris Lattner wrote: > On Mon, 30 Jul 2007, Sarah Thompson wrote: > >> ... can *any* instruction(s) other than load and store cause memory >> reads or writes? >> > > Functions calls can (transitively), This isn't a problem because I'll be picking up those reads and writes as the function executes anyway. > intrinsics can, Would it be feasible to
2015 Nov 19
5
[RFC] Introducing a vector reduction add instruction.
...ion about the intrinsic approach. >>> >>> Yes, I think introducing such a reduction add can let us do pattern recognition >>> of either SAD or dot production (or more?) without introducing any >>> additional intrinsics. >> I agree. Another use case could be POPCOUNT operation. Moreover, as 'reduction add' >> Is being adopted by more targets now a days, reflecting that in LLVM IR as an instruction >> Is a good idea. >> BTW, what is the idea of the syntax and semantic of this operation you have? > > We can introduce a reduce-add f...
2014 May 04
12
[LLVMdev] [RFC] Benchmarking subset of the test suite
...03-09-18-BitFieldTest SingleSource/UnitTests/2003-10-13-SwitchTest SingleSource/UnitTests/2003-10-29-ScalarReplBug SingleSource/UnitTests/2004-02-02-NegativeZero SingleSource/UnitTests/2004-06-20-StaticBitfieldInit SingleSource/UnitTests/2004-11-28-GlobalBoolLayout SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls SingleSource/UnitTests/2005-05-12-Int64ToFP SingleSource/UnitTests/2005-05-13-SDivTwo SingleSource/UnitTests/2005-07-17-INT-To-FP SingleSource/UnitTests/2005-11-29-LongSwitch SingleSource/UnitTests/2006-01-29-SimpleIndirectCall SingleSource/UnitTests/2006-02-04-DivRem SingleSource/UnitTests...
2016 May 18
0
[ANNOUNCE] xcb-proto 1.12
...doc: new expr element listelement-ref xcb-schema: add listelement-ref xinput: ev KeyPress: support list axisvalues xinput: ev ButtonPress, TouchBegin: support list axisvalues xinput: RawEvents: support lists axisvalues and axisvalues_raw xinput: remove TODO-entry for popcount of a list xcbgen: support paramref in the parser schema: add paramref xcb-doc: add paramref xinput: rep GetDeviceMotionEvents: full support xinput: update TODO: remove parametrized structs Merge http://git.demorecorder.com/git/free-sw/xcb/proto branch demorec/Par...
2015 Nov 25
2
[RFC] Introducing a vector reduction add instruction.
...k introducing such a reduction add can let us do >> >>> pattern recognition >> >>> of either SAD or dot production (or more?) without introducing >> >>> any >> >>> additional intrinsics. >> >> I agree. Another use case could be POPCOUNT operation. Moreover, >> >> as 'reduction add' >> >> Is being adopted by more targets now a days, reflecting that in >> >> LLVM IR as an instruction >> >> Is a good idea. >> >> BTW, what is the idea of the syntax and semantic of thi...
2015 Nov 25
2
[RFC] Introducing a vector reduction add instruction.
...ction add can let us do > >> >>> pattern recognition > >> >>> of either SAD or dot production (or more?) without introducing > >> >>> any > >> >>> additional intrinsics. > >> >> I agree. Another use case could be POPCOUNT operation. > >> >> Moreover, > >> >> as 'reduction add' > >> >> Is being adopted by more targets now a days, reflecting that in > >> >> LLVM IR as an instruction > >> >> Is a good idea. > >> >> BTW, wh...
2015 Aug 03
3
[LLVMdev] seeking advice
I recently subscribed to the LLVM and Clang developer mailing lists, and earlier today read a message requesting advice on "Contributing to LLVM Projects". I'm hoping to eventually get involved as well, but with my situation being very different to that described in the referenced thread I got the idea of solliciting advice seperately. If this is not the right place to ask, though,
2020 Nov 05
0
Loop-vectorizer prototype for the EPI Project based on the RISC-V Vector Extension (Scalable vectors)
Hi all, On 11/5/20 10:32 AM, Roger Ferrer Ibáñez wrote: Hi Sjoerd, thanks for pointing us to this intrinsic. I see it returns a mask/predicate type. My understanding is that VPred intrinsics have both a vector length operand and a mask operand. It looks to me that a "popcount" of get.active.lane.mask would correspond to the vector length operand. Then additional "control flow" mask of predicated code would correspond to the mask operand. My intepretation was that get.active.lane.mask allowed targets that do not have a concept of vector length (such as SV...
2011 Dec 01
1
[LLVMdev] [llvm-testresults] bwilson__llvm-gcc_PROD__i386 nightly tester results
...; > 2.28% 0.0790 0.0808 0.0004 > External/SPEC/CINT2000/175_vpr/175_vpr.compile > <http://llvm.org/perf/db_default/simple/nts/380/graph?pset.0=on&test.External%2FSPEC%2FCINT2000%2F175_vpr%2F175_vpr.compile=on> > 2.26% 3.0062 3.0740 0.0051 > SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls.compile > <http://llvm.org/perf/db_default/simple/nts/380/graph?pset.0=on&test.SingleSource%2FUnitTests%2F2005-05-11-Popcount-ffs-fls.compile=on> > 2.24% 0.0447 0.0457 0.0001 > External/SPEC/CFP2006/444_namd/444_namd.compile > <http://llvm.org/perf/db_default/simple...
2012 Feb 19
2
[LLVMdev] Problem While Running Test Suite
...ce/UnitTests/conditional-gnu-ext | * | * | SingleSource/UnitTests/2002-08-02-CastTest | * | * | SingleSource/UnitTests/2002-05-03-NotTest | * | * | SingleSource/UnitTests/2005-05-11-Popcount-ffs-fls | * | * | SingleSource/UnitTests/2009-12-07-StructReturn | * | * | SingleSource/UnitTests/2002-12-13-MishaTest | * | * | SingleSource/UnitTests/printargs...
2020 Nov 05
2
Loop-vectorizer prototype for the EPI Project based on the RISC-V Vector Extension (Scalable vectors)
...ion (Scalable vectors) Hi all, On 11/5/20 10:32 AM, Roger Ferrer Ibáñez wrote: Hi Sjoerd, thanks for pointing us to this intrinsic. I see it returns a mask/predicate type. My understanding is that VPred intrinsics have both a vector length operand and a mask operand. It looks to me that a "popcount" of get.active.lane.mask would correspond to the vector length operand. Then additional "control flow" mask of predicated code would correspond to the mask operand. My intepretation was that get.active.lane.mask allowed targets that do not have a concept of vector length (such as SV...