search for: pmm7

...erence rate. When dividing the core''s clock rate down, C1-clock ramping adjusts the TSC increment so that the TSC appears to continue incrementing at the undivided clock reference rate of the current P-state. BIOS enables and configures the value of the divisor by programming the PMM7 registers in the processor''s integrated Northbridge. The operating system initiates the mechanism by issuing the HLT instruction. As each core in an AMD Dual-core processor has its own clock-grid, only the core that issues the HLT is affected. The adjustment of a core''s...