search for: pmc

...@ -23,6 +23,7 @@ > */ > > #include <subdev/mc.h> > +#include <core/option.h> > > static irqreturn_t > nouveau_mc_intr(int irq, void *arg) > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) > map++; > } > > + if (pmc->use_msi) > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); Register not present everywhere. At the very least, the enabling of MSI should be disallowed on the earlier chipsets where it's not supported. Though, it's perhaps possible that the pci_enable_msi() cal...

...ion. So add a new function which is dedicated to the GPU rail > gating. Also don't refer to the powergate ID since the GPU ID makes no > sense here. > > Signed-off-by: Vince Hsu <vinceh at nvidia.com> To be honest I don't see the point of this patch. You are bloating the PMC interface by introducing another exported function that does nothing different than what the current function already does. If you need a way to assert the clamp I would have expected you to introduce a common function to do this for all power partitions. Other comments inline. Regards, Lucas &...

...eau/core/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c @@ -23,6 +23,7 @@ */ #include <subdev/mc.h> +#include <core/option.h> static irqreturn_t nouveau_mc_intr(int irq, void *arg) @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) map++; } + if (pmc->use_msi) + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); + if (intr) { nv_error(pmc, "unknown intr 0x%08x\n", stat); } @@ -75,6 +79,8 @@ _nouveau_mc_dtor(struct nouveau_object *object) struct nouveau_device *device = nv_device(object); struct nouveau_mc *pmc = (void...

...8] [drm] No driver support for vblank timestamp query. [ 7.170138] [drm] nouveau 0000:06:00.0: ntfy -12 [ 7.170288] [drm] nouveau 0000:06:00.0: 0xD642: Parsing digital output script table [ 7.220570] [drm] nouveau 0000:06:00.0: Restoring VGA fonts [ 7.221181] [drm] nouveau 0000:06:00.0: PMC - unhandled INTR 0x01000000 [ 7.221584] [drm] nouveau 0000:06:00.0: PMC - unhandled INTR 0x01000000 [ 7.221980] [drm] nouveau 0000:06:00.0: PMC - unhandled INTR 0x01000000 [ 7.222372] [drm] nouveau 0000:06:00.0: PMC - unhandled INTR 0x01000000 [ 7.222760] [drm] nouveau 0000:06:00.0: PMC...

...e <subdev/mc.h> > > +#include <core/option.h> > > > > static irqreturn_t > > nouveau_mc_intr(int irq, void *arg) > > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) > > map++; > > } > > > > + if (pmc->use_msi) > > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); > Register not present everywhere. > > At the very least, the enabling of MSI should be disallowed on the > earlier chipsets where it's not supported. Though, it's perhaps > possible...

...; +} + +static int gk20a_pmu_dvfs_target(struct gk20a_pmu_priv *priv, int *state) { struct nvkm_clk *clk = nvkm_clk(priv); @@ -160,40 +396,529 @@ resched: } static int -gk20a_pmu_fini(struct nvkm_object *object, bool suspend) +gk20a_pmu_enable_hw(struct gk20a_pmu_priv *priv, struct nvkm_mc *pmc, bool enable) { - struct nvkm_pmu *pmu = (void *)object; - struct gk20a_pmu_priv *priv = (void *)pmu; + if (enable) { + nv_mask(pmc, 0x000200, 0x00002000, 0x00002000); + nv_rd32(pmc, 0x00000200); + if (nv_wait(priv, 0x0010a10c, 0x00000006, 0x00000000)) + return 0; + nv_mask(pmc, 0x00000200,...

...tegra_powergate_remove_clamping() is not sufficient for the enable function. So add a new function which is dedicated to the GPU rail gating. Also don't refer to the powergate ID since the GPU ID makes no sense here. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- drivers/soc/tegra/pmc.c | 34 +++++++++++++++++++++++----------- include/soc/tegra/pmc.h | 2 ++ 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index a2c0ceb95f8f..7798c530ead1 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -225,...

...on which is dedicated to the GPU rail >> gating. Also don't refer to the powergate ID since the GPU ID makes no >> sense here. >> >> Signed-off-by: Vince Hsu <vinceh at nvidia.com> > To be honest I don't see the point of this patch. > You are bloating the PMC interface by introducing another exported > function that does nothing different than what the current function > already does. > > If you need a way to assert the clamp I would have expected you to > introduce a common function to do this for all power partitions. I thought about ad...

...mu_priv *priv = to_gk20a_priv(pmu); + nv_wr32(pmu, 0x10a014, 0x00000060); + flush_work(&pmu->recv.work); nvkm_timer_alarm_cancel(priv, &priv->alarm); return nvkm_subdev_fini(&pmu->base, suspend); } static int +gk20a_pmu_enable_hw(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc, + bool enable) +{ + if (enable) { + nv_mask(pmc, 0x000200, 0x00002000, 0x00002000); + nv_rd32(pmc, 0x00000200); + if (nv_wait(ppmu, 0x0010a10c, 0x00000006, 0x00000000)) + return 0; + nv_mask(pmc, 0x00000200, 0x2000, 0x00000000); + nv_error(ppmu, "Falcon mem scrubbing timeout\n")...

...> --- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c >> +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c >> @@ -93,8 +93,8 @@ _nouveau_mc_dtor(struct nouveau_object *object) >> { >> struct nouveau_device *device = nv_device(object); >> struct nouveau_mc *pmc = (void *)object; >> - free_irq(device->pdev->irq, pmc); >> - if (pmc->use_msi) >> + free_irq(pmc->irq, pmc); >> + if (nv_device_is_pci(device) && pmc->use_msi) > You should be able to keep the conditional as is. > >> pci_disable_msi(de...

...PU rail > >> gating. Also don't refer to the powergate ID since the GPU ID makes no > >> sense here. > >> > >> Signed-off-by: Vince Hsu <vinceh at nvidia.com> > > To be honest I don't see the point of this patch. > > You are bloating the PMC interface by introducing another exported > > function that does nothing different than what the current function > > already does. > > > > If you need a way to assert the clamp I would have expected you to > > introduce a common function to do this for all power parti...

This is the first set of patches to make Nouveau work on Tegra. Those are only the obvious correctness fixes, a lot of optimization work remains to be done, but at least it's enough to get accel working and let the machine survive a piglit run. A new BO flag is introduced to allow userspace to hint the kernel about possible optimizations. Lucas Stach (6): drm/ttm: recognize ARM arch in

...c..572190c8363b 100644 > --- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c > +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c > @@ -93,8 +93,8 @@ _nouveau_mc_dtor(struct nouveau_object *object) > { > struct nouveau_device *device = nv_device(object); > struct nouveau_mc *pmc = (void *)object; > - free_irq(device->pdev->irq, pmc); > - if (pmc->use_msi) > + free_irq(pmc->irq, pmc); > + if (nv_device_is_pci(device) && pmc->use_msi) You should be able to keep the conditional as is. > pci_disable_msi(device->pdev); > nouveau...

...te) >> { >> struct nvkm_clk *clk = nvkm_clk(priv); >> @@ -160,40 +396,529 @@ resched: >> } >> >> static int >> -gk20a_pmu_fini(struct nvkm_object *object, bool suspend) >> +gk20a_pmu_enable_hw(struct gk20a_pmu_priv *priv, struct nvkm_mc *pmc, >> bool enable) >> { >> - struct nvkm_pmu *pmu = (void *)object; >> - struct gk20a_pmu_priv *priv = (void *)pmu; >> + if (enable) { >> + nv_mask(pmc, 0x000200, 0x00002000, 0x00002000); >> + nv_rd32(pmc, 0x000...

...t;> gating. Also don't refer to the powergate ID since the GPU ID makes no >>>> sense here. >>>> >>>> Signed-off-by: Vince Hsu <vinceh at nvidia.com> >>> To be honest I don't see the point of this patch. >>> You are bloating the PMC interface by introducing another exported >>> function that does nothing different than what the current function >>> already does. >>> >>> If you need a way to assert the clamp I would have expected you to >>> introduce a common function to do this for...

...void *arg) >>>>>>>> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >>>>>>>> > map++; >>>>>>>> > } >>>>>>>> > >>>>>>>> > + if (pmc->use_msi) >>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>> Register not present everywhere. >>>>>>>> >>>>>>>> At the very least, the enabling of MSI should b...

...base) spin_unlock_irqrestore(&mc->lock, flags); } -static void +void gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) { struct gp100_mc *mc = gp100_mc(base); @@ -87,13 +87,14 @@ gp100_mc = { }; int -gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, + int index, struct nvkm_mc **pmc) { struct gp100_mc *mc; if (!(mc = kzalloc(sizeof(*mc), GFP_KERNEL))) return -ENOMEM; - nvkm_mc_ctor(&gp100_mc, device, index, &mc->base); + nvkm_mc_ctor(func, d...

...gt;>> > @@ -43,6 +44,9 @@ nouveau_mc_intr(int irq, void *arg) >>>>>>>>>> > map++; >>>>>>>>>> > } >>>>>>>>>> > >>>>>>>>>> > + if (pmc->use_msi) >>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); >>>>>>>>>> Register not present everywhere. >>>>>>>>>> >>>>>>>>>> At the very lea...

...ct nvkm_pmu *ppmu, const struct firmware *fw); > + > +static int > +gk20a_pmu_load_firmware(struct nvkm_pmu *ppmu, const struct firmware **pfw); > +static int gk20a_init_pmu_setup_sw(struct nvkm_pmu *ppmu); > +static int gk20a_init_pmu_setup_hw1(struct nvkm_pmu *ppmu, struct nvkm_mc *pmc); > +static void gk20a_pmu_intr(struct nvkm_subdev *subdev); > > +static void gk20a_pmu_pgob(struct nvkm_pmu *ppmu, bool enable); > struct gk20a_pmu_dvfs_data { > int p_load_target; > int p_load_max; > int p_smooth; > unsigned int avg_load; &...

...ouveau_mc_intr(int irq, void *arg) > >>>>>>>>>>> > map++; > >>>>>>>>>>> > } > >>>>>>>>>>> > > >>>>>>>>>>> > + if (pmc->use_msi) > >>>>>>>>>>> > + nv_wr08(pmc->base.base.parent, 0x00088068, 0xff); > >>>>>>>>>>> Register not present everywhere. > >>>>>>>>>>> > >>>>>>...