Displaying 9 results from an estimated 9 matches for "pllvals".
2017 Jul 29
0
[PATCH] nouveau: Fix declarations with incorrect variables.
...rm/nouveau/dispnv04/hw.h b/drm/nouveau/dispnv04/hw.h
index 3a2be47f..2afda90a 100644
--- a/drm/nouveau/dispnv04/hw.h
+++ b/drm/nouveau/dispnv04/hw.h
@@ -43,7 +43,7 @@ void NVSetOwner(struct drm_device *, int owner);
void NVBlankScreen(struct drm_device *, int head, bool blank);
int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype,
struct nvkm_pll_vals *pllvals);
-int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
+int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv);
int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype);
void nouv...
2017 Nov 27
1
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...2) & 1;
sim_data.memory_width = 64;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index b985990..0c9bdf0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ int domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dwor...
2017 Dec 19
1
[PATCH V4 09/26] drm/nouveau: deprecate pci_get_bus_and_slot()
...2) & 1;
sim_data.memory_width = 64;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index b985990..0c9bdf0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ int domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dwor...
2017 Jan 20
0
[PATCH] nv1a,nv1f/disp: fix memory clock rate retrieval
...amp; 0xf;
if (!mpllP)
mpllP = 4;
@@ -232,7 +233,7 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
uint32_t clock;
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
- return clock;
+ return clock / 1000;
}
ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
--
2.10.2
2017 Nov 22
0
[PATCH V2 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...2) & 1;
sim_data.memory_width = 64;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index b985990..8806b1b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
{
struct nvkm_pll_vals pllvals;
int ret;
+ u32 domain;
+
+ domain = pci_domain_nr(dev->pdev->bus);
if (plltype == PLL_MEMORY &&
(dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
uint32_t mpllP;
-
- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ pci_read_config_dwor...
2017 Nov 27
0
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...h = 64;
> diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
> index b985990..0c9bdf0 100644
> --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
> +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
> @@ -216,12 +216,15 @@
> {
> struct nvkm_pll_vals pllvals;
> int ret;
> + int domain;
> +
> + domain = pci_domain_nr(dev->pdev->bus);
>
> if (plltype == PLL_MEMORY &&
> (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
> uint32_t mpllP;
> -
> - pci_read_config_dword(pci_get_bus_and_slot...
2009 Nov 23
2
[PATCH 1/3] drm/nouveau: Update the CRTC arbitration parameters on FB depth switch.
...uct drm_display_mod
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &dev_priv->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
- struct drm_framebuffer *fb = crtc->fb;
struct nouveau_pll_vals *pv = ®p->pllvals;
struct pll_lims pll_lim;
- int vclk, arb_burst, arb_fifo_lwm;
if (get_pll_limits(dev, nv_crtc->index ? VPLL2 : VPLL1, &pll_lim))
return;
@@ -130,8 +128,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
if (dev_priv->chipset > 0x40 &&a...
2009 Aug 13
9
[PATCHv2 01/10] drm/nouveau: Fix a lock up at NVSetOwner with nv11.
It seems it was only locking up in the context of
nouveau_hw_save_vga_fonts, when it actually did something (because
the console wasn't already in graphics mode).
Signed-off-by: Francisco Jerez <currojerez at riseup.net>
---
drivers/gpu/drm/nouveau/nouveau_hw.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c
2009 Aug 12
14
[PATCH 00/12] TV-out modesetting kernel patches.
This patch series adds TV-out modesetting support to the KMS
implementation.
I've tried to test it on all the hardware I've got at hand (that is
nv11, nv17, nv34, nv35, nv40, nv4b) with every possible output
combination; I believe it has reached a mergeable state, however it
depends on some commits from drm-next that haven't got into Linus'
tree yet, if you agree to merge this