Displaying 3 results from an estimated 3 matches for "pll_vpll0".
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pll_vpll1
2013 Jan 04
1
[PATCH] drm/nouveau/clock: fix support for more than 2 monitors on nve0
.../include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
index c345097..b2f3d4d 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
@@ -38,6 +38,8 @@ enum nvbios_pll_type {
PLL_UNK42 = 0x42,
PLL_VPLL0 = 0x80,
PLL_VPLL1 = 0x81,
+ PLL_VPLL2 = 0x82,
+ PLL_VPLL3 = 0x83,
PLL_MAX = 0xff
};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
index f6962c9..7c96262 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++...
2017 Jan 10
0
[bug report] drm/nouveau/devinit: move simple pll setting routines to devinit
...if (!ret) {
52 nvkm_error(subdev, "failed pll calculation\n");
53 return ret;
This should probably be a negative error code instead of "ret"?
54 }
55
56 switch (info.type) {
57 case PLL_VPLL0:
58 case PLL_VPLL1:
59 nvkm_wr32(device, info.reg + 0, 0x10000611);
60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
61 nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) |
62...
2020 Aug 27
0
[PATCH] drm/nouveau: remove redundant check
...)
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->client.device;
struct nvkm_clk *clk = nvxx_clk(device);
- struct nvkm_bios *bios = nvxx_bios(device);
struct nvbios_pll pll_lim;
struct nvkm_pll_vals pv;
enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
- if (nvbios_pll_parse(bios, pll, &pll_lim))
+ if (nouveau_hw_get_pllvals(dev, pll, &pv))
return;
- nouveau_hw_get_pllvals(dev, pll, &pv);
if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
pv.N1 >= pll_lim.vco1.min_n && pv...