Displaying 5 results from an estimated 5 matches for "pll_memory".
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2017 Nov 27
1
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
.../gpu/drm/nouveau/dispnv04/hw.c
index b985990..0c9bdf0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
 {
 	struct nvkm_pll_vals pllvals;
 	int ret;
+	int domain;
+
+	domain = pci_domain_nr(dev->pdev->bus);
 
 	if (plltype == PLL_MEMORY &&
 	    (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
 		uint32_t mpllP;
-
-		pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+				      0x6c, &mpllP);
 		mpllP = (mpllP >> 8) &...
2017 Dec 19
1
[PATCH V4 09/26] drm/nouveau: deprecate pci_get_bus_and_slot()
.../gpu/drm/nouveau/dispnv04/hw.c
index b985990..0c9bdf0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
 {
 	struct nvkm_pll_vals pllvals;
 	int ret;
+	int domain;
+
+	domain = pci_domain_nr(dev->pdev->bus);
 
 	if (plltype == PLL_MEMORY &&
 	    (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
 		uint32_t mpllP;
-
-		pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+				      0x6c, &mpllP);
 		mpllP = (mpllP >> 8) &...
2017 Jan 10
0
[bug report] drm/nouveau/devinit: move simple pll setting routines to devinit
...nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
    61                  nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P  << 28) |
    62                                                              (M2 << 16) | N2);
    63                  break;
    64          case PLL_MEMORY:
    65                  nvkm_mask(device, info.reg + 0, 0x01ff0000,
    66                                                  (P << 22) |
    67                                                  (info.bias_p << 19) |
    68                                                  (P << 16))...
2017 Nov 22
0
[PATCH V2 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
.../gpu/drm/nouveau/dispnv04/hw.c
index b985990..8806b1b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@
 {
 	struct nvkm_pll_vals pllvals;
 	int ret;
+	u32 domain;
+
+	domain = pci_domain_nr(dev->pdev->bus);
 
 	if (plltype == PLL_MEMORY &&
 	    (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
 		uint32_t mpllP;
-
-		pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+				      0x6c, &mpllP);
 		mpllP = (mpllP >> 8) &...
2017 Nov 27
0
[PATCH V3 10/29] drm/nouveau: deprecate pci_get_bus_and_slot()
...00644
> --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
> +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
> @@ -216,12 +216,15 @@
>  {
>  	struct nvkm_pll_vals pllvals;
>  	int ret;
> +	int domain;
> +
> +	domain = pci_domain_nr(dev->pdev->bus);
>  
>  	if (plltype == PLL_MEMORY &&
>  	    (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
>  		uint32_t mpllP;
> -
> -		pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
> +		pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
> +				      0x6c, &mpllP);
&...