Displaying 2 results from an estimated 2 matches for "plabe".
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2011 Mar 22
2
theora-dev Digest, Vol 80, Issue 6
...ck throw RLE, how after this stage i
can separately write different AC for its AC-plane? For example after
zig-zag we have this:
AC0 =1 AC(1..61) =0 AC62 =1
after RLE we have:
(0,1)(61,1)
How add zero-ACs coeff to AC(1..61) planes? Or i skip them in this planes
and add store only non-zero coeff to plabes?
Thanks
P.S. please give me more critique. More critique - better implementation
On 22 March 2011 22:00, <theora-dev-request at xiph.org> wrote:
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2011 Mar 22
5
FPGA encode stages flow diagram
Good day!
I create diagram of encoder process. Using it i create implementation of
encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing
stages?
Here is blog http://developer-fpga.blogspot.com/
Here is picture of encoding stage 1
https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg
Here is picture of encoding stage 2