search for: pl_to_div

...lg_calc_mnp() clk/gk20a: rename enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract pl_to_div clk/gk20a: split gk20a_clk_new() clk/gk20a: set lowest frequency during init() clk/gk20a: share reusable structures/functions clk/gm20b: add basic driver Vince Hsu (1): volt/gk20a: share reusable members & functions drm/nouveau/include/nvkm/subdev/clk.h | 1 + drm/nouveau/includ...

...(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) + +#include <linux/types.h> +#include <linux/clk.h> +#include <linux/delay.h> + +#include <subdev/clock.h> +#include <subdev/timer.h> + +#include <nouveau_platform.h> + +static const u8 pl_to_div[] = { +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, +}; + +/* All frequencies in Mhz */ +struct gk20a_clk_pllg_params { + u32 min_freq, max_freq; + u32 min_vco, max_vco; + u32 min_u, max_u; + u32 min_m, max_m; + u32 m...

...in a separate patch)? > + > +#include <linux/types.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > + > +#include <subdev/clock.h> > +#include <subdev/timer.h> > + > +#include <nouveau_platform.h> > + > +static const u8 pl_to_div[] = { > +/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ > +/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, > +}; > + > +/* All frequencies in Mhz */ > +struct gk20a_clk_pllg_params { > + u32 min_freq, max_freq; > + u32 min_vco, max_vco; > +...

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

...cient which I could >> not find in the NVE0 driver, > Interesting. Can you give more details on how "PL" works exactly, > we'd been operating on the assumption (mainly inherited from code that > appeared in xf86-video-nv) that it was always a straight division. The pl_to_div table in clock/gk20a.c should give the right coefficients, but I have seen contradictory information in our docs. Let me ask the right people so we can get to the bottom of this. > >> - Some registers that NVE0 expects to find are not present on GK20A (e.g. >> 0x137120 and 0x13...