search for: piplineable

Hi, how can I use R in a pipline like this $ ./generate-data | R --script-file=Script.R | ./further-analyse-data > result.dat Assume a column based output of ./generate-data, e.g. something like: 1 1 1 2 4 8 3 9 27 4 16 64 The R commands that process the data should come from Script.R and should print to stdout (Script.R could for example calculate the square of every entry or calculate

I added support for supplying file name(s) in the command line for i/o in the examples in "vorbis/examples". If no arguments are supplied, then the current filter pipline mode (stdin/stdout for i/o) is used. The primary reason for this, is to be able to run these in a debugging session. Additionally, in the encoder example, instead of a hard-coded "data" chunk offset of 44,

Hello, My out-of-tree target features some high latency instructions (let's call them FXLV). When an FXLV issues, it reserves its destination register and execution continues; if a subsequent instruction attempts to read or write that register, the pipline will stall until the FXLV completes. I have attempted to encode this constraint in the machine scheduler (excerpt at bottom of email).

On 7/10/13 3:43 PM, Cristianno Martins wrote: > Hello John, > > What opt command line arguments are you using? I'm not using opt. I'm manually scheduling a pipline within a tool. The code looks like this: PassManager pm; MyAlias * aa = new MyAlias(); pm.add(aa); pm.add(new MyAliasUsingPass()); Both MyAlias and MyAliasUsingPass are now ModulePass'es. MyAlias is an alias

Since introducing the new TargetTransformInfo analysis, there has been some confusion over the role of target heuristics in IR passes. A few patches have led to interesting discussions. To centralize the discussion, until we get some documentation and better APIs in place, let me throw out an oversimplified Straw Man for a new pass pipline. It serves two purposes: (1) an overdue reorganization of

On 7/16/2013 11:38 PM, Andrew Trick wrote: > Since introducing the new TargetTransformInfo analysis, there has been some confusion over the role of target heuristics in IR passes. A few patches have led to interesting discussions. > > To centralize the discussion, until we get some documentation and better APIs in place, let me throw out an oversimplified Straw Man for a new pass pipline.

Hi Lorenzo, I’ll answer the first question you have: > I would like to use llvm-mca to estimate the IPC of a given code region. I am interested in the library version

On Tue, Mar 12, 2019 at 10:59:09AM +0800, Jason Wang wrote: > > On 2019/3/12 ??2:14, David Miller wrote: > > From: "Michael S. Tsirkin" <mst at redhat.com> > > Date: Mon, 11 Mar 2019 09:59:28 -0400 > > > > > On Mon, Mar 11, 2019 at 03:13:17PM +0800, Jason Wang wrote: > > > > On 2019/3/8 ??10:12, Christoph Hellwig wrote: > > >

On Tue, Mar 12, 2019 at 10:59:09AM +0800, Jason Wang wrote: > > On 2019/3/12 ??2:14, David Miller wrote: > > From: "Michael S. Tsirkin" <mst at redhat.com> > > Date: Mon, 11 Mar 2019 09:59:28 -0400 > > > > > On Mon, Mar 11, 2019 at 03:13:17PM +0800, Jason Wang wrote: > > > > On 2019/3/8 ??10:12, Christoph Hellwig wrote: > > >

...y one of those archs needed explicit cache flushes, where > > vhost worked correctly so far.. so it kinds of proofs your point of > > giving up being the safe choice). > > What double hit? If there's no cache to flush then cache flush is a > no-op. It's also a highly piplineable no-op because the CPU has the L1 > cache within easy reach. The only event when flush takes a large > amount time is if we actually have dirty data to write back to main > memory. I've heard people complaining that on some microarchitectures even no-op cache flushes are relatively ex...

Hi Sjoerd, On Fri, May 3, 2019 at 8:19 AM Sjoerd Meijer via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > I read that out-of-order cores are supported. How about in-order cores? > Would it be easy/difficult to add support for that? > > Cheers, > Sjoerd. > > I don't think that it would be difficult to support in-order superscalar cores. However, it would

> Out of curiosity, what hardware/drivers do? (It also failed with my > radeon(4) card.) I have a geffo 4 ti 4200 AGP 4x OpenGL 1.3 hardaware support, GL_ARB_fragment must be an extension of OpenGL 2, also Windows nvidia driver lack of this extension. Looking at the source code written by David Reveman the GL_ARB_fragment_program it's used when loading the bump mapping effects. I've

...y one of those archs needed explicit cache flushes, where > > vhost worked correctly so far.. so it kinds of proofs your point of > > giving up being the safe choice). > > What double hit? If there's no cache to flush then cache flush is a > no-op. It's also a highly piplineable no-op because the CPU has the L1 > cache within easy reach. The only event when flush takes a large > amount time is if we actually have dirty data to write back to main > memory. The double hit is in parisc copy_to_user_page: #define copy_to_user_page(vma, page, vaddr, dst, src, len) \...

..., > > > > where vhost worked correctly so far.. so it kinds of proofs your > > > > point of giving up being the safe choice). > > > > > > What double hit? If there's no cache to flush then cache flush is > > > a no-op. It's also a highly piplineable no-op because the CPU has > > > the L1 cache within easy reach. The only event when flush takes a > > > large amount time is if we actually have dirty data to write back > > > to main memory. > > > > I've heard people complaining that on some microarchit...

Hello John, What opt command line arguments are you using? If you follow this link<http://llvm.org/docs/Passes.html#no-aa-no-alias-analysis-always-returns-may-alias>, you can see that -no-aa is the default alias analysis implementation if you do not manually specify which AA passes you want to use. Note that you can pass as many different implementations of AA as you want, and each of them

Dear All, I'm trying to add a new alias analysis to the alias analysis group in LLVM 3.2. This new pass is linked statically into a tool that lives outside the LLVM source tree, so I'm trying to avoid making patches to the LLVM sources. I've added the INITIALIZE_AG_PASS_BEGIN() and INITIALIZE_AG_PASS_END() code to the pass, manually scheduled it before the

Hi All, I would like to use llvm-mca to estimate the IPC of a given code region. I am interested in the library version (https://reviews.llvm.org/D50929?id=162210 <https://reviews.llvm.org/D50929?id=162210>) but I have troubles understanding how to use it. Could you please point me to some documentations or (better) some code examples if any? Reading the documentation

On Jul 29, 2013, at 9:05 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 7/16/2013 11:38 PM, Andrew Trick wrote: >> Since introducing the new TargetTransformInfo analysis, there has been some confusion over the role of target heuristics in IR passes. A few patches have led to interesting discussions. >> >> To centralize the discussion, until we get

...he flushes, >>>>> where vhost worked correctly so far.. so it kinds of proofs your >>>>> point of giving up being the safe choice). >>>> What double hit? If there's no cache to flush then cache flush is >>>> a no-op. It's also a highly piplineable no-op because the CPU has >>>> the L1 cache within easy reach. The only event when flush takes a >>>> large amount time is if we actually have dirty data to write back >>>> to main memory. >>> I've heard people complaining that on some microarchitec...

...he flushes, >>>>> where vhost worked correctly so far.. so it kinds of proofs your >>>>> point of giving up being the safe choice). >>>> What double hit? If there's no cache to flush then cache flush is >>>> a no-op. It's also a highly piplineable no-op because the CPU has >>>> the L1 cache within easy reach. The only event when flush takes a >>>> large amount time is if we actually have dirty data to write back >>>> to main memory. >>> I've heard people complaining that on some microarchitec...