Displaying 6 results from an estimated 6 matches for "pipe_texture_1d_array".
2014 May 10
1
[PATCH] nv50, nvc0: fix blit 3d path for 1d array textures
...d8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -698,6 +698,12 @@ nv50_blitter_make_fp(struct pipe_context *pipe,
tc = ureg_DECL_fs_input(
ureg, TGSI_SEMANTIC_GENERIC, 0, TGSI_INTERPOLATE_LINEAR);
+ if (ptarg == PIPE_TEXTURE_1D_ARRAY) {
+ /* Adjust coordinates. Depth is in z, but TEX expects it to be in y. */
+ tc = ureg_swizzle(tc, TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
+ TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Z);
+ }
+
data = ureg_DECL_temporary(ureg);
if (tex_s) {
--
1.8.5.5
2014 Feb 19
0
[PATCH] nv50: enable cube map array texture support
.../nouveau/nv50/nv50_tex.c
index 6784821..5cfce3a 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -115,12 +115,12 @@ nv50_create_texture_view(struct pipe_context *pipe,
addr = mt->base.address;
- if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
- mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
+
+ if (mt->base.base.array_size > 1) {
+ /* there doesn't seem to be a base layer field in TIC */
addr += view->pipe.u.tex.first_layer *...
2016 Feb 15
2
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...TIC2_4_TEXTURE_TYPE_TWO_D;
> + break;
> + case PIPE_TEXTURE_3D:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
> + break;
> + case PIPE_TEXTURE_CUBE:
> + depth /= 6;
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
> + break;
> + case PIPE_TEXTURE_1D_ARRAY:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
> + break;
> + case PIPE_TEXTURE_2D_ARRAY:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
> + break;
> + case PIPE_TEXTURE_CUBE_ARRAY:
> + depth /= 6;
> + tic[4] |= GM107_TIC2_4_TEX...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...se PIPE_TEXTURE_RECT:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
+ break;
+ case PIPE_TEXTURE_3D:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
+ break;
+ case PIPE_TEXTURE_CUBE:
+ depth /= 6;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
+ break;
+ case PIPE_TEXTURE_1D_ARRAY:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
+ break;
+ case PIPE_TEXTURE_2D_ARRAY:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
+ break;
+ case PIPE_TEXTURE_CUBE_ARRAY:
+ depth /= 6;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
+ break;
+...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...+ break;
>> + case PIPE_TEXTURE_3D:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
>> + break;
>> + case PIPE_TEXTURE_CUBE:
>> + depth /= 6;
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
>> + break;
>> + case PIPE_TEXTURE_1D_ARRAY:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
>> + break;
>> + case PIPE_TEXTURE_2D_ARRAY:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
>> + break;
>> + case PIPE_TEXTURE_CUBE_ARRAY:
>> + depth /= 6;
>> +...
2016 Feb 15
24
[PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb
From: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Ben Skeggs <bskeggs at redhat.com>
---
src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++
1 file changed, 279 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h