search for: pipe_surfac

...Draw () at tri.c:83 #11 0xf7ecdc54 in processWindowWorkList (window=0x8051200) at glut_event.c:1302 #12 0xf7ecdd3a in __glutProcessWindowWorkLists () at glut_event.c:1354 #13 0xf7ecddb1 in glutMainLoop () at glut_event.c:1375 #14 0x08048fd8 in main (argc=1, argv=0xfff760e4) at tri.c:132 The struct pipe_surface used there contains garbage: (gdb) print *fb->cbufs[0] $4 = {buffer = 0xf7d901a0, format = -136773216, status = 1, clear_value = 0, width = 189, height = 181, block = {size = 4, width = 1, height = 1}, nblocksx = 189, nblocksy = 181, stride = 768, layout = 0, offset = 0, refcount = 0, usa...

This patch series silences some unknown cap warnings and fixes up coding style (patch 1+4). The most important part of this series are the two patches in the middle. They rework the state_fb code, so that we are able to render to not 64 byte aligned targets, as this is the only real use-case for render temporaries this allows us to drop temp code completely and simplifies a lot

...ipe) extern void nv04_init_state_functions(struct nv04_context *nv04); extern void nv04_init_surface_functions(struct nv04_context *nv04); -extern void nv04_screen_init_miptree_functions(struct pipe_screen *screen); /* nv04_clear.c */ extern void nv04_clear(struct pipe_context *pipe, struct pipe_surface *ps, diff --git a/src/gallium/drivers/nv04/nv04_miptree.c b/src/gallium/drivers/nv04/nv04_miptree.c index e0a6948..d30b046 100644 --- a/src/gallium/drivers/nv04/nv04_miptree.c +++ b/src/gallium/drivers/nv04/nv04_miptree.c @@ -1,64 +1,133 @@ #include "pipe/p_state.h" #include "pipe...

...ipe) extern void nv04_init_state_functions(struct nv04_context *nv04); extern void nv04_init_surface_functions(struct nv04_context *nv04); -extern void nv04_screen_init_miptree_functions(struct pipe_screen *screen); /* nv04_clear.c */ extern void nv04_clear(struct pipe_context *pipe, struct pipe_surface *ps, diff --git a/src/gallium/drivers/nv04/nv04_miptree.c b/src/gallium/drivers/nv04/nv04_miptree.c index e0a6948..74c2250 100644 --- a/src/gallium/drivers/nv04/nv04_miptree.c +++ b/src/gallium/drivers/nv04/nv04_miptree.c @@ -1,64 +1,138 @@ #include "pipe/p_state.h" #include "pipe...

.../drivers/nv50/nv50_clear.c index db44a9d..45d0a00 100644 --- a/src/gallium/drivers/nv50/nv50_clear.c +++ b/src/gallium/drivers/nv50/nv50_clear.c @@ -26,10 +26,15 @@ #include "nv50_context.h" +#include "util/u_pack_color.h" + void -nv50_clear(struct pipe_context *pipe, struct pipe_surface *ps, - unsigned clearValue) +nv50_clear(struct pipe_context *pipe, unsigned buffers, + const float *rgba, double depth, unsigned stencil) { + struct pipe_surface *ps = NULL; + /* silenced 'used uninitialized' warning by setting NULL, + * GCC doesn't know it can't actually...

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for

...NG (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2); BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); @@ -250,7 +253,7 @@ nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst, if (format < 0) return 1; - WAIT_RING (chan, 12); + MARK_RING (chan, 12, 4); BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -315,7...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- The pipe_surface miscount caused issues for my (failed) attempt at getting vdpau to work with pmpeg. src/gallium/drivers/nouveau/nouveau_video.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_video.h b/src/gallium/drivers/nouveau/nouveau_video.h in...

...ot, > + num_views, views); > +} > + > +static void > +tegra_set_shader_resources(struct pipe_context *pcontext, > + unsigned start, > + unsigned count, > + struct pipe_surface **resources) > +{ > + struct tegra_context *context = to_tegra_context(pcontext); > + > + context->gpu->set_shader_resources(context->gpu, start, count, > + resources); > +} > + > +static void > +tegra_set_ver...

...NG (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2); BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); @@ -250,7 +253,7 @@ nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst, if (format < 0) return 1; - WAIT_RING (chan, 12); + MARK_RING (chan, 12, 4); BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -315,7...

...surf.base.texture = &mip.base.base; >> + mip.level[0].tile_mode = 0; >> + mip.level[0].pitch = surf.width * 4; >> + mip.base.domain = NOUVEAU_BO_VRAM; >> + mip.base.bo = dec->mbring; >> + context->clear_render_target(context, (struct pipe_surface *)&surf, &color, 0, 0, 64, 4760); >> + surf.offset = dec->vpring->size / 2 - 0x1000; >> + surf.width = 1024; >> + surf.height = 1; >> + mip.level[0].pitch = surf.width * 4; >> + mip.base.bo = dec->vpring; >> + conte...

...NG (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2); BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); @@ -250,7 +253,7 @@ nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst, if (format < 0) return 1; - WAIT_RING (chan, 12); + MARK_RING (chan, 12, 4); BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2); OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD); OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); @@ -315,7...

...um/drivers/nouveau/nv50/nv50_resource.c index 7fbb0a9..d289b4a 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_resource.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_resource.c @@ -68,6 +68,8 @@ nv50_surface_create(struct pipe_context *pipe, struct pipe_resource *pres, const struct pipe_surface *templ) { + /* surfaces are assumed to be miptrees all over the place. */ + assert(pres->target != PIPE_BUFFER); if (unlikely(pres->target == PIPE_BUFFER)) return nv50_surface_from_buffer(pipe, pres, templ); return nv50_miptree_surface_new(pipe, pres, templ); diff --git a...

...; i++) + views[i] = tegra_sampler_view_unwrap(pviews[i]); + + context->gpu->set_sampler_views(context->gpu, shader, start_slot, + num_views, views); +} + +static void +tegra_set_shader_resources(struct pipe_context *pcontext, + unsigned start, + unsigned count, + struct pipe_surface **resources) +{ + struct tegra_context *context = to_tegra_context(pcontext); + + context->gpu->set_shader_resources(context->gpu, start, count, + resources); +} + +static void +tegra_set_vertex_buffers(struct pipe_context *pcontext, + unsigned start_slot, + unsigned num_buff...

...rly benefit from some cleanup). > If a driver implements this just with util_resource_copy_region, it is > possible there are performance regressions, since some (certainly not > all) state trackers used a quad blitter instead if this wasn't available. > The u_blit code still uses a pipe_surface as destination, which should > probably be changed at some point too but the change was already big > enough imho. > > Historically, blits had to operate on surfaces IIRC since there actually > were surfaces in gallium not backed by a pipe_resource (then > pipe_texture) but those...

...&mip.base.base; >>> + mip.level[0].tile_mode = 0; >>> + mip.level[0].pitch = surf.width * 4; >>> + mip.base.domain = NOUVEAU_BO_VRAM; >>> + mip.base.bo = dec->mbring; >>> + context->clear_render_target(context, (struct pipe_surface *)&surf, &color, 0, 0, 64, 4760); You can drop the typecast here s/(struct pipe_surface *)&surf/&surf.base/ >>> + surf.offset = dec->vpring->size / 2 - 0x1000; >>> + surf.width = 1024; >>> + surf.height = 1; >>> + mip.l...

...vel = 0; > + surf.base.texture = &mip.base.base; > + mip.level[0].tile_mode = 0; > + mip.level[0].pitch = surf.width * 4; > + mip.base.domain = NOUVEAU_BO_VRAM; > + mip.base.bo = dec->mbring; > + context->clear_render_target(context, (struct pipe_surface *)&surf, &color, 0, 0, 64, 4760); > + surf.offset = dec->vpring->size / 2 - 0x1000; > + surf.width = 1024; > + surf.height = 1; > + mip.level[0].pitch = surf.width * 4; > + mip.base.bo = dec->vpring; > + context->clear_render_targ...

Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- src/gallium/drivers/nouveau/nouveau_stateobj.h | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_stateobj.h b/src/gallium/drivers/nouveau/nouveau_stateobj.h index b595405..28f483f 100644 --- a/src/gallium/drivers/nouveau/nouveau_stateobj.h +++

https://bugs.freedesktop.org/show_bug.cgi?id=109330 Bug ID: 109330 Summary: GL_ALPHA_BITS set to non-zero with EGL_PLATFORM_GBM_MESA Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:

..._ref(nvc0->screen->base.fence.current, &buf->fence); + nouveau_fence_ref(nvc0->screen->base.fence.current, &buf->fence_wr); + nvc0->dirty |= NVC0_NEW_FRAMEBUFFER; +} + +static void nvc0_clear_depth_stencil(struct pipe_context *pipe, struct pipe_surface *dst, unsigned clear_flags, @@ -1363,4 +1513,5 @@ nvc0_init_surface_functions(struct nvc0_context *nvc0) pipe->flush_resource = nvc0_flush_resource; pipe->clear_render_target = nvc0_clear_render_target; pipe->clear_depth_stencil = nvc0_clear_depth_ste...