search for: pipe_bind_sampler_view

The number of vertex buffers has nothing to do with the number of bound constbufs. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.4 10.3" <mesa-stable at lists.freedesktop.org> --- src/gallium/drivers/nouveau/nv50/nv50_context.c | 5 +++-- src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git

The main patches are from Christoph. Unfortunately they're a little beyond my understanding of all the vertex-related details, but they generally seemed fine. I'm just going to push these unless someone steps up to review them. Christoph Bumiller (2): nvc0: add support for indirect drawing nvc0: fix translate path for PRIM_RESTART_WITH_DRAW_ARRAYS Ilia Mirkin (1): nouveau: check if

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for

...buffer->base.interlaced = true; By storing the number of planes, will be able to demagic some constants later on buffer->num_planes = 2; > + > + memset(&templ, 0, sizeof(templ)); > + templ.target = PIPE_TEXTURE_2D_ARRAY; > + templ.depth0 = 1; > + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; > + templ.format = PIPE_FORMAT_R8_UNORM; > + templ.width0 = align(template->width, 2); > + templ.height0 = align(template->height, 4) / 2; > + templ.flags = NV50_RESOURCE_FLAG_VIDEO; > + templ.array_size = 2; > + > + cfg.nv50.tile_mo...

...+39,9 @@ > * C: render target (color), blendable only on nvc0 > * D: scanout/display target, blendable > * Z: depth/stencil > - * V: vertex fetch > * I: image / surface, implies T > */ > -#define U_V PIPE_BIND_VERTEX_BUFFER > +#define U_V 0 > #define U_T PIPE_BIND_SAMPLER_VIEW > #define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | > PIPE_BIND_COMPUTE_RESOURCE > #define U_TR PIPE_BIND_RENDER_TARGET | U_T > @@ -103,10 +102,7 @@ > (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \ > (NV50_TIC_TYPE_##t2 &l...

...drivers/nouveau/nv50/nv50_formats.c @@ -39,10 +39,9 @@ * C: render target (color), blendable only on nvc0 * D: scanout/display target, blendable * Z: depth/stencil - * V: vertex fetch * I: image / surface, implies T */ -#define U_V PIPE_BIND_VERTEX_BUFFER +#define U_V 0 #define U_T PIPE_BIND_SAMPLER_VIEW #define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE #define U_TR PIPE_BIND_RENDER_TARGET | U_T @@ -103,10 +102,7 @@ (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \ (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT...

...o does that. I find that incredibly confusing. It's always 2, and they are of diff size. I prefer my bike-shed color :) > >> + >> + memset(&templ, 0, sizeof(templ)); >> + templ.target = PIPE_TEXTURE_2D_ARRAY; >> + templ.depth0 = 1; >> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >> + templ.format = PIPE_FORMAT_R8_UNORM; >> + templ.width0 = align(template->width, 2); >> + templ.height0 = align(template->height, 4) / 2; >> + templ.flags = NV50_RESOURCE_FLAG_VIDEO; >> + templ.array_size = 2; >> + &...

...y confusing. It's always 2, > and they are of diff size. I prefer my bike-shed color :) > >> >>> + >>> + memset(&templ, 0, sizeof(templ)); >>> + templ.target = PIPE_TEXTURE_2D_ARRAY; >>> + templ.depth0 = 1; >>> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >>> + templ.format = PIPE_FORMAT_R8_UNORM; >>> + templ.width0 = align(template->width, 2); >>> + templ.height0 = align(template->height, 4) / 2; >>> + templ.flags = NV50_RESOURCE_FLAG_VIDEO; >>> + templ.array_si...

This CAP will determine whether ARB_framebuffer_object can be enabled. The nv30 driver does not allow mixing swizzled and linear zsbuf/cbuf textures. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/docs/source/screen.rst | 3 +++ src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 +

...get_sampler_view_components = nv84_video_buffer_sampler_view_components; + buffer->base.get_surfaces = nv84_video_buffer_surfaces; + buffer->base.interlaced = true; + + memset(&templ, 0, sizeof(templ)); + templ.target = PIPE_TEXTURE_2D_ARRAY; + templ.depth0 = 1; + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; + templ.format = PIPE_FORMAT_R8_UNORM; + templ.width0 = align(template->width, 2); + templ.height0 = align(template->height, 4) / 2; + templ.flags = NV50_RESOURCE_FLAG_VIDEO; + templ.array_size = 2; + + cfg.nv50.tile_mode = 0x20; + cfg.nv50.memtype = 0...

...get_sampler_view_components = nv84_video_buffer_sampler_view_components; + buffer->base.get_surfaces = nv84_video_buffer_surfaces; + buffer->base.interlaced = true; + + memset(&templ, 0, sizeof(templ)); + templ.target = PIPE_TEXTURE_2D_ARRAY; + templ.depth0 = 1; + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; + templ.format = PIPE_FORMAT_R8_UNORM; + templ.width0 = align(template->width, 2); + templ.height0 = align(template->height, 4) / 2; + templ.flags = NV50_RESOURCE_FLAG_VIDEO; + templ.array_size = 2; + + cfg.nv50.tile_mode = 0x20; + cfg.nv50.memtype = 0...

From: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> --- src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which