Displaying 3 results from an estimated 3 matches for "pinsr".
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2011 Feb 15
0
[LLVMdev] LLVMdev Digest, Vol 80, Issue 13
...gt; register
Given what we know of Larrabee and speculating that the "Knights" family
is likely a derivative of it, it's safe to assume that future Intel
architectures will be much more like traditional vector machines. That
means gather/scatter, element indexing, etc. The existing PINSR/PEXTR
and shuffle instructions already allow a degree of element indexing.
Note that the existing LLVM vector types already have insert/extract
operators.
Unifying array and vector and generalizing the result would open a lot
of optimization opportunities.
-Dave
2011 Oct 17
0
[LLVMdev] LLVM Build Bot failure on llmv-x86_64-ubuntu
Looks like pinsr is not being generated on llvm-x86_64-ubuntu...
jabbey at davinci:~$ /home/jabbey/src/osuosl/buildbot/sandbox/llvm-x86_64-ubuntu/llvm-x86_64-ubuntu/llvm/Debug+Asserts/bin/llc < /home/jabbey/src/osuosl/buildbot/sandbox/llvm-x86_64-ubuntu/llvm-x86_64-ubuntu/llvm/test/CodeGen/X86/mmx-pinsrw.ll -...
2011 Feb 14
8
[LLVMdev] LLVMdev Digest, Vol 80, Issue 13
Andrew,
your response highlights a naming problem in LLVM,
which is that "array" and "vector"
mean the same thing in normal computer language and compiler theory
usage, so it is
inconvenient and misleading within LLVM to give one a very specific
meaning that is different
from the other....
to the LLVM developers I would suggest using the term