search for: physreg

Displaying 20 results from an estimated 264 matches for "physreg".

2016 Aug 23
2
Help in understanding physreg LiveVariables
...l;font-size:10.5pt" ><div dir="ltr" >Matthias,</div> <div dir="ltr" > </div> <div dir="ltr" >Thanks for the response.</div> <div dir="ltr" > </div> <div dir="ltr" >In short, I'm using physregs because my current design, in some cases, needs to create an entirely new var/reg during instruction legalization. This value can be passed from one basic block to another and, therefore, must be added as a live-in to a number of basic blocks. I was unable to find a way to add a virt reg as a live...
2016 Aug 23
2
Help in understanding physreg LiveVariables
...r" >This is consistent with the behaviour I'm witnessing, but I don't understand why it's designed this way. I am developing an out-of-tree backend and I have the following scenario:</div> <div dir="ltr" > </div> <div dir="ltr" > -physreg X marked as a live-in for a successor MBB (A.K.A., a live-out of the current block)<br> -physreg X is a member of an allocatable reg-class<br> -the only reference to physreg X in the current block is a<strong>: %physregX<def> = COPY %vreg43<kill></strong&g...
2018 Jan 08
2
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%').
When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of a particular architecture. - The $ was somewhat arbitrary b...
2015 Dec 10
3
Allowing virtual registers after register allocation
To say this first: This whole discussion about using virtregs until emit or having growable physregs is hard to argue without actually having experience trying to go either way. Problems when using virtregs throughout the backend until emit time: - The MC layer is using MCPhysReg (which is an uint16_t) and would need retrofitting to support virtregs - VirtRegs are assumed to have a definition, p...
2012 Sep 10
3
[LLVMdev] Assert in LiveInterval update
...'ve got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could introduce some subtle bugs. Cheers, Lang. On Wed, Sep 5, 2012 at 4:07 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Sep 2, 2012, at 11:52 PM, Lang Hames <lhames at gmail.com> wrote: >...
2008 Feb 07
1
[LLVMdev] [PATCH] fix warning: 'NumFolded' defined but not used
lib/CodeGen/RegAllocLocal.cpp:38: warning: 'NumFolded' defined but not used This has been introduced because of r46821. However, maybe removing just the variable isn't enought, because the comments in the section that got modified by 46821 are not optimal: if (PhysReg) { // Register is available, allocate it! assignVirtToPhysReg(VirtReg, PhysReg); } else { // No registers available. // If we can fold this spill into this instruction, do so now. This comment says that something should be folded. SmallVector<unsigned, 2> Ops; Op...
2018 Jan 08
0
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%').
On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate > from vregs to allow people to differentiate vregs/physregs even if they > don't know all the physreg names of a particular architecture. > - The $...
2016 Aug 23
2
Help in understanding physreg LiveVariables
...hat I don't know how to pass a newly created virtual register from one MBB/DAG to another. Tyler From: Matthias Braun <mbraun at apple.com> To: Tyler Kenney/Marlborough/IBM at IBMUS Cc: llvm-dev at lists.llvm.org Date: 08/23/2016 04:43 PM Subject: Re: [llvm-dev] Help in understanding physreg LiveVariables Sent by: mbraun at apple.com On Aug 23, 2016, at 1:38 PM, Tyler Kenney <tjkenney at us.ibm.com> wrote: Matthias, Thanks for the response. In short, I'm using physregs because my current design, in some cases, needs to create an enti...
2009 Mar 25
2
[LLVMdev] Register allocation of stack slots
...s) - allocation for e.g. function arguments passed by the stack work fine. For example, the debug output of the initialization of several stack slots is the following: 1 : entry: 2 : %reg1074<def> = movC 0 3 : Store: store <fi#18>, 0, %R0<kill> 4 : Remembering SS#18 in physreg R0 5 : store <fi#18>, 0, %R0<kill> 6 : Reusing SS#18 from physreg R0 for vreg1075 instead of reloading into physreg R0 7 : store <fi#9>, 0, %R0, Mem:ST(2,2) [sig5069_nl + 0] 8 : Reusing SS#18 from physreg R0 for vreg1076 instead of reloading into physreg R0 9 : store...
2017 Jun 05
3
VirtRegMap invariant: no reserved physical registers?
Hey all, I've found a bug in either the PBQP register allocator or in VirtRegRewriter. I'm observing this assertion in VirtRegRewriter::rewrite() fail: unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM->getPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly:...
2012 Sep 04
0
[LLVMdev] Assert in LiveInterval update
...s at gmail.com> wrote: > Hi Sergei, > > I just fixed the broken test case for PR13719 with r163107, but from the debugging output you've posted it suspect it won't fix your test case. > > Your analysis looks good - findLastUseBefore(..) doesn't appear to be handling physregs. I'm surprised that isn't causing more failures. I'll see if I can find a failing case in the LLVM test-suite (it's been a while since I ran live-interval-update over all of it) and try out your modifications to findLastUseBefore. I think Sergei's analysis is correct, but you...
2017 Dec 25
2
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%').
...ve decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil used for external symbols ('$') for the ampersand ('&') and re-purpose dollar-sign for physregs so that physregs have the dollar-sign sigil and vregs have the percentage ('%') sigil: essentially: BL *&*__divsi3 ... ... $eax = ... %123 = ... %vregFooBar = ... I have an initial patch attached (replaces '$' for '&' for external symbols). Hoping to open so...
2009 Dec 07
1
[LLVMdev] 2.5 Regalloc Assert
I am hitting this assert in LLVM 2.5: /// spillPhysRegAroundRegDefsUses - Spill the specified physical register /// around all defs and uses of the specified interval. void LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, unsigned PhysReg, VirtRegMap &vrm) { unsigned SpillReg =...
2007 Jul 10
1
[LLVMdev] VirtRegMap GLIBCXX assert
The following code in VirtRegMap.cpp is asserting in the C++ library because back() is called on an empty container: /// addLastUse - Add the last use information of all stack slots whose /// values are available in the specific register. void addLastUse(unsigned PhysReg, MachineInstr *Use) { std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(PhysReg); while (I != PhysRegsAvailable.end() && I->first == PhysReg) { int Slot = I->second; I++; std::map<int, SSInfo>::iterator II = SpillSlot...
2016 Jan 13
2
Allowing virtual registers after register allocation
...Duplicate is currently disabled for wasm via TargetMachine::RequiresStructuredCFG() MachineCopyPropagation: currently has checks (even for release builds) that there are no vregs, and is currently disabled manually for wasm and NVPTX. ExpandPostRAPseudos has 2 parts: LowerSubregToReg expects only physregs and has asserts to ensure it. LowerCopy simply calls TargetInstrInfo::copyPhysReg() to emit the instructions for lowering COPYs (wasm's implementation of copyPhysReg() just handles vregs) and is otherwise agnostic. MachineBlockPlacement doesn't do anything at all to any MachineInstrs itse...
2017 Dec 26
0
Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%').
...roperly implement a syntax for MIR named vregs we > first need to reorganized the sigils used for physical registers and > external symbols so our proposal is to swap the sigil used for external > symbols ('$') for the ampersand ('&') and re-purpose dollar-sign for > physregs so that physregs have the dollar-sign sigil and vregs have the > percentage ('%') sigil: > > essentially: > > BL *&*__divsi3 ... > > ... > > $eax = ... > > %123 = ... > > %vregFooBar = ... > > > I have an initial patch attached (replaces...
2016 Jan 22
2
Allowing virtual registers after register allocation
...or wasm via > TargetMachine::RequiresStructuredCFG() > > MachineCopyPropagation: currently has checks (even for release builds) > that there are no vregs, and is currently disabled manually for wasm and > NVPTX. > > ExpandPostRAPseudos has 2 parts: LowerSubregToReg expects only physregs > and has asserts to ensure it. > LowerCopy simply calls TargetInstrInfo::copyPhysReg() to emit the > instructions for lowering COPYs (wasm's implementation of copyPhysReg() > just handles vregs) and is otherwise agnostic. > > MachineBlockPlacement doesn't do anything at...
2012 Sep 10
0
[LLVMdev] Assert in LiveInterval update
...'ve got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could these trigger on interaction with a '0' interval? That could introduce some subtle bugs. Right. Regunits are numbered independently from physregs, starting from 0. Each regunit corresponds to one or two physregs, the 'roots', which are typically leaf registers. The mapping...
2013 Apr 19
2
[LLVMdev] MachineOperand SubReg
...ister operand, is getReg() guaranteed to be the >> "most super" register with getSubReg() providing the specific >> subregister information for the operand? If so then for my current >> purposes it seems I don't need to worry about subregisters at all. > > For physregs, getSubReg() is guaranteed to be 0. It is only used for > virtual registers. Aha! So for physregs, getSubReg() will simply be the exact physical register defined. Cool, that'll work. > Yep, there is no such thing as a 'most super' register. The register > aliasing graph is...
2016 Jan 06
1
[PATCH] nv50/ir: don't touch degree on physreg RIG nodes
...r_ra.cpp @@ -1129,9 +1129,11 @@ GCRA::doCoalesce(ArrayList& insns, unsigned int mask) void GCRA::RIG_Node::addInterference(RIG_Node *node) { - this->degree += relDegree[node->colors][colors]; - node->degree += relDegree[colors][node->colors]; - + // don't add degree for physregs since they won't go through simplify() + if (this->reg < 0) + this->degree += relDegree[node->colors][colors]; + if (node->reg < 0) + node->degree += relDegree[colors][node->colors]; this->attach(node, Graph::Edge::CROSS); } -- 2.4.10