search for: physbase

...diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index cafae86813ae..0ce6453c9272 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -53,6 +53,7 @@ extern unsigned long __startup_secondary_64(void); extern void startup_64_setup_env(unsigned long physbase); extern void early_idt_setup_early_handler(unsigned long physaddr); extern void early_load_idt(void); +extern void early_idt_setup(unsigned long physbase); extern void __init do_early_exception(struct pt_regs *regs, int trapnr); #ifdef CONFIG_X86_INTEL_MID diff --git a/arch/x86/include/asm/s...

...lude <asm/microcode.h> #include <asm/kasan.h> #include <asm/fixmap.h> +#include <asm/realmode.h> /* * Manage page tables very early on. @@ -513,6 +514,8 @@ void __init x86_64_start_reservations(char *real_mode_data) */ void __head startup_64_setup_env(unsigned long physbase) { + unsigned long gsbase; + /* Load GDT */ startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); native_load_gdt(&startup_gdt_descr); @@ -521,4 +524,8 @@ void __head startup_64_setup_env(unsigned long physbase) asm volatile("movl %%eax, %%ds\n"...

...lude <asm/microcode.h> #include <asm/kasan.h> #include <asm/fixmap.h> +#include <asm/realmode.h> /* * Manage page tables very early on. @@ -513,6 +514,8 @@ void __init x86_64_start_reservations(char *real_mode_data) */ void __head startup_64_setup_env(unsigned long physbase) { + unsigned long gsbase; + /* Load GDT */ startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); native_load_gdt(&startup_gdt_descr); @@ -521,4 +524,8 @@ void __head startup_64_setup_env(unsigned long physbase) asm volatile("movl %%eax, %%ds\n"...

...ry(idt, n, &desc); > +} > +#endif > + > +static struct desc_ptr early_idt_descr __initdata = { > + .size = IDT_TABLE_SIZE - 1, > + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */, > +}; > + > +void __init early_idt_setup(unsigned long physbase) > +{ > + void __maybe_unused *handler; > + gate_desc *idt; > + > + idt = fixup_pointer(idt_table, physbase); > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + /* VMM Communication Exception */ > + handler = fixup_pointer(vc_no_ghcb, physbase); > + set_early_idt_handler(idt, X8...

...ry(idt, n, &desc); > +} > +#endif > + > +static struct desc_ptr early_idt_descr __initdata = { > + .size = IDT_TABLE_SIZE - 1, > + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */, > +}; > + > +void __init early_idt_setup(unsigned long physbase) > +{ > + void __maybe_unused *handler; > + gate_desc *idt; > + > + idt = fixup_pointer(idt_table, physbase); > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + /* VMM Communication Exception */ > + handler = fixup_pointer(vc_no_ghcb, physbase); > + set_early_idt_handler(idt, X8...

...er) +{ + struct idt_data data; + gate_desc desc; + + init_idt_data(&data, n, handler); + idt_init_desc(&desc, &data); + native_write_idt_entry(bringup_idt_table, n, &desc); +} +#endif + /* This runs while still in the direct mapping */ static void startup_64_load_idt(unsigned long physbase) { struct desc_ptr *desc = fixup_pointer(&bringup_idt_descr, physbase); + void __maybe_unused *handler; + +#ifdef CONFIG_AMD_MEM_ENCRYPT + /* VMM Communication Exception */ + handler = fixup_pointer(vc_no_ghcb, physbase); + set_bringup_idt_handler(X86_TRAP_VC, handler); +#endif desc->...

...tatic inline unsigned long get_debugctlmsr(void) { diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 0ce6453c9272..bbd40dd20be7 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -54,6 +54,7 @@ extern void startup_64_setup_env(unsigned long physbase); extern void early_idt_setup_early_handler(unsigned long physaddr); extern void early_load_idt(void); extern void early_idt_setup(unsigned long physbase); +extern void early_load_tss(void); extern void __init do_early_exception(struct pt_regs *regs, int trapnr); #ifdef CONFIG_X86_INTEL_MID...

..._desc; + + set_tssldt_descriptor(&tss_desc, (unsigned long)tss, DESC_TSS, + __KERNEL_TSS_LIMIT); + native_write_gdt_entry(gdt, GDT_ENTRY_TSS, &tss_desc, DESC_TSS); + + asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); +} + void __head early_idt_setup(unsigned long physbase) { gate_desc *idt = fixup_pointer(idt_table, physbase); diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 4d84a0c72e36..7f2d5e14db73 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -220,6 +220,9 @@ SYM_CODE_START(secondary_startup_64) */ movq...

On Mon, Aug 31, 2020 at 11:45:41AM +0200, Borislav Petkov wrote: > On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > > +#ifdef CONFIG_AMD_MEM_ENCRYPT > > + /* VMM Communication Exception */ > > + handler = fixup_pointer(vc_no_ghcb, physbase); > > + set_early_idt_handler(idt, X86_TRAP_VC, handler); > > This function is used only once AFAICT - you might just as well add its > three-lined body here and save yourself the function definition and > ifdeffery above... True, but having a separate function might be handy wh...

...6ba0427b0..5c09f50ecf1c 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -50,6 +50,8 @@ extern unsigned long __startup_64(unsigned long physaddr, struct boot_params *bp extern unsigned long __startup_secondary_64(void); extern void startup_64_setup_env(unsigned long physbase); extern int early_make_pgtable(unsigned long address); +extern void early_idt_setup_early_handler(unsigned long physaddr); +extern void early_load_idt(void); #ifdef CONFIG_X86_INTEL_MID extern void x86_intel_mid_early_setup(void); @@ -66,6 +68,7 @@ static inline void x86_ce4100_early_setup(vo...

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build

From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or

...rapnr) early_make_pgtable(native_read_cr2())) return; +#ifdef CONFIG_AMD_MEM_ENCRYPT + if (trapnr == X86_TRAP_VC && + handle_vc_boot_ghcb(regs)) + return; +#endif + early_fixup_exception(regs, trapnr); } @@ -572,6 +578,11 @@ static void startup_64_load_idt(unsigned long physbase) /* This is used when running on kernel addresses */ void early_setup_idt(void) { +#ifdef CONFIG_AMD_MEM_ENCRYPT + /* VMM Communication Exception */ + set_bringup_idt_handler(X86_TRAP_VC, vc_boot_ghcb); +#endif + bringup_idt_descr.address = (unsigned long)bringup_idt_table; native_load_idt(&...

...struct msi_desc *entry, *tmp; diff -r 7750906b06b3 -r 31f09a5e24cf xen/arch/x86/physdev.c --- a/xen/arch/x86/physdev.c Wed Sep 24 10:23:51 2008 +0100 +++ b/xen/arch/x86/physdev.c Wed Sep 24 12:36:55 2008 +0100 @@ -26,17 +26,11 @@ ioapic_guest_write( ioapic_guest_write( unsigned long physbase, unsigned int reg, u32 pval); - -extern struct hw_interrupt_type pci_msi_type; - static int get_free_pirq(struct domain *d, int type, int index) { int i; - if ( d == NULL ) - return -EINVAL; - - ASSERT(spin_is_locked(&d->arch.irq_lock)); + ASSERT(spin_is_locked(&...

There is a BUG_ON() at xen/arch/x86/physdev.c:169 which appears to be dependent upon guest behavior (should close event channel before un-mapping pirq), rather than on internal hypervisor state. In 2.6.18, this likely goes unnoticed because pci_device_shutdown() only calls all the driver shutdown routines. In newer kernels, however, it also calls pci_msi_shutdown() and pci_msix_shutdown(), which

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the first public post of the patch-set to enable Linux to run under SEV-ES enabled hypervisors. The code is mostly feature-complete, but there are still a couple of bugs to fix. Nevertheless, given the size of the patch-set, I think it is about time to ask for initial feedback of the changes that come with it. To better understand the code here is a quick explanation of SEV-ES first.

Hi, here is the next version of changes to enable Linux to run as an SEV-ES guest. The code was rebased to v5.7-rc3 and got a fair number of changes since the last version. What is SEV-ES ============== SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted State' and means a hardware feature of AMD processors which hides the register state of VCPUs to the hypervisor by