Displaying 3 results from an estimated 3 matches for "phys_addr_bit".
2015 Apr 17
4
[PATCH 2/6] instmem/gk20a: refer to IOMMU physical translation bit
...; --- a/drm/nouveau/nvkm/subdev/instmem/gk20a.c
> +++ b/drm/nouveau/nvkm/subdev/instmem/gk20a.c
> @@ -89,6 +89,7 @@ struct gk20a_instmem_priv {
> struct nvkm_mm *mm;
> struct iommu_domain *domain;
> unsigned long iommu_pgshift;
> + unsigned long iommu_phys_addr_bit;
>
> /* Only used by DMA API */
> struct dma_attrs attrs;
> @@ -169,8 +170,8 @@ gk20a_instobj_dtor_iommu(struct gk20a_instobj_priv *_node)
> r = list_first_entry(&_node->mem->regions, struct nvkm_mm_node,
> rl_entry);...
2015 Apr 16
15
[PATCH 0/6] map big page by platform IOMMU
Hi,
Generally the the imported buffers which has memory type TTM_PL_TT are
mapped as small pages probably due to lack of big page allocation. But the
platform device which also use memory type TTM_PL_TT, like GK20A, can
*allocate* big page though the IOMMU hardware inside the SoC. This is a try
to map the imported buffers as big pages in GMMU by the platform IOMMU. With
some preparation work to
2015 Apr 16
2
[PATCH 6/6] mmu: gk20a: implement IOMMU mapping for big pages
...quot;IOMMU: IOVA=0x%016llx-> IOMMU -> PA=%016llx\n",
> + (u64)(node->offset + i) << PAGE_SHIFT, (u64)(*list));
> + }
> +
> + addr = (u64)node->offset << PAGE_SHIFT;
> + addr |= BIT_ULL(plat->gpu->iommu.phys_addr_bit);
> +
> + gk20a_vm_map(vma, pgt, mem, pte, addr);
> +
> + p = *priv;
> + p->node = node;
> + p->iova = node->offset << PAGE_SHIFT;
> +}
> +
> +static void
> +gk20a_vm_map_sg_iommu(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
>...