search for: phyregs

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Did you mean: physregs
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
...erstand arbitrary machine >> instrs in the face of physreg subregs. This lays the groundwork for >> handling vreg subregs, but won't solve it directly. > > Is the work Evan doing a prerequisite for supporting vreg subregs? Sort of. vreg subregs work can start before I finish phyregs subregs support. But unless there are no live-in registers nothing can possibly work. > Is there a PR for the feature Evan is working on? You filed it. PR1306. :-) > >>> Is any of this kind of work planned? The addition of those >>> MRegisterInfo functions has me curi...
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
Thanks for the detailed response. On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote: > Right. Evan is currently focusing on getting the late stages of > the code > generator (e.g. livevars) to be able to understand arbitrary machine > instrs in the face of physreg subregs. This lays the groundwork for > handling vreg subregs, but won't solve it directly. Is the work Evan
2007 Apr 24
2
[LLVMdev] Register based vector insert/extract
...>>> instrs in the face of physreg subregs. This lays the groundwork for >>> handling vreg subregs, but won't solve it directly. >> >> Is the work Evan doing a prerequisite for supporting vreg subregs? > > Sort of. vreg subregs work can start before I finish phyregs subregs > support. But unless there are no live-in registers nothing can > possibly work. > >> Is there a PR for the feature Evan is working on? > > You filed it. PR1306. :-) Ah! I didn't realize that the issue would have such far reaching consequences. >>>>...
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 8:44 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Hal Finkel" <hfinkel at anl.gov> > *Cc: *"llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" < > matze at braunis.de>, "Mehdi
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Dear Mentors, Please help me to understand our plan to implement Interprocedural Register allocator by propogating register usage info. While writing this mail I am considering all previous discussion over llvm-dev and IRC. 1) A MachineFunction pass to be executed POST-RA to collect the information about the used Registers. 2) An Immutable pass which will store reg usage info collected by
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > Dear Mentors, > > Please help me to understand our plan to implement Interprocedural Register allocator by propogating register usage info. While writing this mail I am considering all previous discussion over llvm-dev and IRC. > > 1) A MachineFunction pass to be executed POST-RA to
2016 May 25
3
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
> On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > On Wed, May 25, 2016 at 10:08 AM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote: > >> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com <mailto:vivekvpandya at gmail.com>> wrote: >> >> Dear
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 10:08 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > Dear Mentors, > > Please help me to understand our plan to implement Interprocedural > Register allocator by propogating register usage info. While writing this > mail I am considering all previous
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
Sent from my iPhone > On May 24, 2016, at 11:04 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > >> On Wed, May 25, 2016 at 10:46 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: >> >>> On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote: >>> >>> >>> >>> On Wed, May 25,
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 10:46 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > > On May 24, 2016, at 10:08 PM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > > On Wed, May 25, 2016 at 10:08 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 24, 2016, at 9:17 PM, vivek pandya <vivekvpandya at gmail.com> wrote:
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message ----- > From: "Mehdi Amini" <mehdi.amini at apple.com> > To: "vivek pandya" <vivekvpandya at gmail.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" > <llvm-dev at lists.llvm.org>, "Matthias Braun" <matze at braunis.de>, > "Quentin Colombet" <qcolombet at
2016 May 25
0
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
----- Original Message ----- > From: "vivek pandya" <vivekvpandya at gmail.com> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Matthias Braun" > <matze at braunis.de>, "Mehdi Amini" <mehdi.amini at apple.com>, "Quentin > Colombet" <qcolombet at
2016 May 25
2
[GSoC 2016] Interprocedural Register Allocation - Introduction and Feedback
On Wed, May 25, 2016 at 3:53 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > ------------------------------ > > *From: *"vivek pandya" <vivekvpandya at gmail.com> > *To: *"Quentin Colombet" <qcolombet at apple.com> > *Cc: *"Hal Finkel" <hfinkel at anl.gov>, "llvm-dev" <llvm-dev at lists.llvm.org>, >