search for: phieliminate

Dear all, I'm working on an exploratory backend on llvm. In the instruction set I'm using I have an instruction (called DECJNZ) that decrements a register and, if the decremented value is not zero, jumps (with a relative jump) to a given offset. I've described in tablegen this instruction as follow: def DECJNZ : Instruction { let Namespace = "MyTarget"; let

On Jul 4, 2012, at 5:35 AM, Philipp Brüschweiler <blei42 at gmail.com> wrote: > Hi everyone > > I'm hitting an assertion in PHIElimination.cpp:375. > > "Terminator instructions cannot use virtual registers unless" > "they are the first terminator in a block!" > > I was looking at the code around that location a bit and have not found > a

So what is the status about LiveVariables. Is there a plan to remove it? After searching in old lvm-dev-mails it is mentioned that LiveVariable still exists due to one pass needing it. And a comment in TargetPassConfig.cpp indicates that the pass in question is TwoAddressInstruction: // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed

Hi everyone I'm hitting an assertion in PHIElimination.cpp:375. "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!" I was looking at the code around that location a bit and have not found a reason why this assertion has to hold, except for a comment: // In our final twist, we have to decide which instruction

On Wed, Jul 25, 2012 at 12:48 AM, Michele Scandale <michele.scandale at gmail.com> wrote: > Dear all, > > I'm working on an exploratory backend on llvm. In the instruction set I'm using > I have an instruction (called DECJNZ) that decrements a register and, if the > decremented value is not zero, jumps (with a relative jump) to a given offset. > > I've

Il 25/07/2012 10:07, Eli Friedman ha scritto: > On Wed, Jul 25, 2012 at 12:48 AM, Michele Scandale > <michele.scandale at gmail.com> wrote: >> Dear all, >> >> I'm working on an exploratory backend on llvm. In the instruction set I'm using >> I have an instruction (called DECJNZ) that decrements a register and, if the >> decremented value is not

Hello, all, I want to implement the register allocation algorithm described in the paper "Register Allocation via Coloring of Chordal Graphs, APLAS'05" in LLVM. This is a graph coloring algorithm that can find an optimal coloring of the interference graph in most of the cases. I've downloaded LLVM last week, and started studying the code. Basically, I have to implement: 1) A

On Sep 18, 2012, at 1:45 PM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some

Where is the liveness analysis pass? I have been looking for days but cannot find anything. I just want to know transfer variables in and out of basic blocks, that are calculated using simple data flow equations. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180920/529bce15/attachment.html>

On Sat, 29 Apr 2006, Fernando Magno Quintao Pereira wrote: > I want to implement the register allocation algorithm described in the > paper "Register Allocation via Coloring of Chordal Graphs, APLAS'05" in > LLVM. This is a graph coloring algorithm that can find an optimal coloring > of the interference graph in most of the cases. I've downloaded LLVM last > week,

Hi, I am working on a backend for a CGRA architecture with advanced predicate support (as on EPIC machines and as first used in the OpenIMPACT compiler). Until last month, the backend was working fine, but since the r161643 commit by stoklund, my backend doesn't work anymore. I think I noticed some related commits later on, and the assertion I get on the latest trunk (r164162) differs from

Hello. Could you please tell me how can I optimize with the back end (llc) the following piece of assembly code generated by llc: // NOTE: my processor accepts loops in the form of REPEAT(num_times)..END_REPEAT R0 = ... REPEAT(256) R5 = R0; // basically unnecessary reg. copy REPEAT(256) R10 = LS[R4]; R2 = LS[R5]; R4 =

What guarantees, if any, does the scheduler make when two selection nodes are linked by a Flag type? Can I expect the machine instructions that are selected from the two nodes to be scheduled consecutively? I'm trying to implement code generation for SELECT_CC nodes in a back end that I'm working on. The compare operations on the architecture communicate via bits in a global status

I'm debugging a problem with a custom pass and I was surprised to discover that LiveIntervalAnalysis depends on PHIElimination. Why is that so? Intervals could be useful for all sorts of things beyond register allocation. Just curious. Is there something about the design of LiveIntervals that it needs the out-of-SSA conversion? -Dave

Hi, I am a newbie to llvm. I am wondering what approach is used when coming out of SSA form. I also appreciate pointers on where to look in the source code for this phase. Best regards, Ram Ramshankar -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120824/87feb1d3/attachment.html>

On 24 August 2012 02:27, Ramanarayanan, Ramshankar <Ramshankar.Ramanarayanan at amd.com> wrote: > Hi, > > > > I am a newbie to llvm. I am wondering what approach is used when coming out > of SSA form. I also appreciate pointers on where to look in the source code > for this phase. > lib/CodeGen/PHIElimination.cpp is probably what you want. > > Best regards,

On Feb 8, 2013, at 4:45 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > On Feb 8, 2013, at 4:37 PM, Cameron Zwarich <zwarich at apple.com> wrote: > >> I'll try doing that. Did you ever add a way to update LiveIntervals quickly after splitting an edge or will that have to finally be added? I can skip the critical edge splitting for now. > > That

Hi, I would like to have the llvm code modified so as to obtain the amount of spill code generated, for each basic block. Basically what would be helpful would be something like a code for a target which has the same instruction set as LLVM itself. Only extra input I would be providing would be the number of registers. The intention is to analyze the type of applications that stress the

> > Hello, llvmers. Could someone explain me a little about the opt tool? I am > > having problems to load a MachineFunctionPass using opt. I have this pass: > > MachineFunctionPass's cannot be used as part of opt, they can only be used > as part of LLC. Further, you have to explicitly modify the target you are > interested in to add it to the pass manager for that

Dear llvm guys, I am trying to add the BreakCriticalEdges pass to my application. I tried to add it to the PNE pass (e.g. PHIElimination.cpp - AU.addRequiredID(BreakCriticalEdgesID); ), but I get this error: llc -f -regalloc=simple Base1Sum.bc -o simple.s ----------------------------------------------- llc: PassManagerT.h:387: void llvm::PassManagerT<Trait>::markPassUsed(const