search for: pgt

...u/drm/nouveau/core/subdev/vm/base.c index 77c67fc..e66fb77 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c @@ -362,7 +362,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, vm->fpde = offset >> (vmm->pgt_bits + 12); vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); - vm->pgt = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); if (!vm->pgt) { kfree(vm); return...

When I list a directory within the linux OS, appears like this: ... -rwxr--r--. 1 root pgt.cxt 7,2K Nov 25 14:33 New Text OpenDocument.odt ... At smb.conf is of this way: [global] workgroup = PGT server string = Descricao security = DOMAIN obey pam restrictions = Yes ... registry shares = Yes idmap uid = 1000-20000 idmap gid = 100...

.../vm/base.c > index 77c67fc..e66fb77 100644 > --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c > +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c > @@ -362,7 +362,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, > vm->fpde = offset >> (vmm->pgt_bits + 12); > vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); > > - vm->pgt = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL); > + vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); > if (!vm->pgt)...

...type; + int big = shift != vmm->spg_shift; u32 offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; + u32 bits = shift - 12; + u32 num = length >> shift; u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; u32 max = 1 << (vmm->pgt_bits - bits); @@ -98,7 +99,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, for_each_sg(mem->sg->sgl, sg, mem->sg->nen...

...2 offset = vma->node->offset + (delta >> 12); > > - u32 bits = vma->node->type - 12; > > - u32 num = length >> vma->node->type; > > + u32 bits = shift - 12; > > + u32 num = length >> shift; > > u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; > > u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; > > u32 max = 1 << (vmm->pgt_bits - bits); > > @@ -98,7 +99,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, > > > > for_...

...offset = vma->node->offset + (delta >> 12); - u32 bits = vma->node->type - 12; - u32 num = length >> vma->node->type; + u32 shift = vma->node->type; + u32 order = PAGE_SHIFT - shift; + u32 num = length >> PAGE_SHIFT; u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; - u32 max = 1 << (vmm->pgt_bits - bits); - unsigned m, sglen; - u32 end, len; + u32 pte = offset & ((1 << vmm->pgt_bits) - 1); + u32 max = 1 << vmm->pgt_bits; + u32...

...have to say it''s really a good design and implementation IMHO, > especially the parts about the clear hierarchy for each smfn,decision > table and how to support 32nopae in a rather elegant way. However, I > have several questions to discuss with you.:-) > 1) It seems XI shadow pgt reserve all of the possible resources at the > early stage for HVM domain(the first time to create the asi). It could > be quite proper to reserve the smfns and sptis. However, do we really > need to reserve one snapshot page for each smfn at first and retain it > until the HVM domain i...

...->spg_shift; > u32 offset = vma->node->offset + (delta >> 12); > - u32 bits = vma->node->type - 12; > - u32 num = length >> vma->node->type; > + u32 bits = shift - 12; > + u32 num = length >> shift; > u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; > u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; > u32 max = 1 << (vmm->pgt_bits - bits); > @@ -98,7 +99,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, > > for_each_sg(mem->sg->sg...

...fset + (delta >> 12); >> > - u32 bits = vma->node->type - 12; >> > - u32 num = length >> vma->node->type; >> > + u32 bits = shift - 12; >> > + u32 num = length >> shift; >> > u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; >> > u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; >> > u32 max = 1 << (vmm->pgt_bits - bits); >> > @@ -98,7 +99,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, >> &gt...

Hi, Generally the the imported buffers which has memory type TTM_PL_TT are mapped as small pages probably due to lack of big page allocation. But the platform device which also use memory type TTM_PL_TT, like GK20A, can *allocate* big page though the IOMMU hardware inside the SoC. This is a try to map the imported buffers as big pages in GMMU by the platform IOMMU. With some preparation work to

...u32 bits = vma->node->type - 12; > - u32 num = length >> vma->node->type; > + u32 shift = vma->node->type; > + u32 order = PAGE_SHIFT - shift; > + u32 num = length >> PAGE_SHIFT; > u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; > - u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; > - u32 max = 1 << (vmm->pgt_bits - bits); > - unsigned m, sglen; > - u32 end, len; > + u32 pte = offset & ((1 << vmm->pgt_bits)...

...ref[NVDEV_SUBDEV_BAR]); > > - ret = nouveau_gpuobj_new(nv_object(priv), NULL, > - (nv_device_resource_len(device, 3) >> 12) * 8, > - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, > - &vm->pgt[0].obj[0]); > - vm->pgt[0].refcount[0] = 1; > - if (ret) > - return ret; > + /* > + * Bootstrap page table lookup. > + */ > + if (bar == 3) { > + ret = nouveau_gpuobj_new(nv_object(priv), NULL, > +...

...t() > will never be called on these ? Correct. all cards before the nv50 family have no real vm. the BAR used for vram is just an identity mapping, not the entirety of VRAM may be accessible to the system. > - In vm/base.c this construct appears regulary: > > struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; > > Which makes me believe we have separate page tables for small vs. large > pages (in card mmu) (though I assume big is always 0 on nv40 unless > missed something, I want to make sure I'm not breaking everything > else...). > > Thus I assume th...

.../subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c index 0f0d3a5..d83489c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c @@ -34,7 +34,7 @@ struct nv50_vmmgr_priv { spinlock_t lock; }; -void +static void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, struct nouveau_gpuobj *pgt[2]) { @@ -76,7 +76,7 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) return phys; } -void +static void nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, struct nouveau_mem *mem, u32...

...ret = nouveau_vm_new(device, 0, bar_len, 0, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (nv_device_resource_len(device, 3) >> 12) * 8, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, - &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; + /* + * Bootstrap page table lookup. + */ + if (bar == 3) { + ret = nouveau_gpuobj_new(nv_object(priv), NULL, + (bar_len >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &vm->pgt[0].obj[0]); + vm-&g...

...struct nvkm_mmu base; > +}; > + > +struct gk20a_mmu_iommu_mapping { > + struct nvkm_mm_node *node; > + u64 iova; > +}; > + > +extern const u8 gf100_pte_storage_type_map[256]; > + > +static void > +gk20a_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, > + struct nvkm_mem *mem, u32 pte, u64 list) > +{ > + u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; > + u64 phys; > + > + pte <<= 3; > + phys = gf100_vm_addr(vma, list, mem->memtype, target); > + > +...

...; PAGE_SHIFT; end = pte + sglen; Seems to imply an assumption here that the "pte" is in multiple of PAGE_SHIFT, but afaik, it's not. So further down, we do: for (m = 0; m < len; m++) { dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); vmm->map_sg(vma, pgt, mem, pte, 1, &addr); num--; pte++; But in fact, inside vmm->map_sg, with the current code, we will have incremented pte by more than 1 ... so we basically lose track here. if (num == 0) goto finish; } if (unlikely(end >= max)) { pde++; pte...

...ret = nouveau_vm_new(device, 0, bar_len, 0, &vm); if (ret) return ret; atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (nv_device_resource_len(device, 3) >> 12) * 8, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, - &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; - if (ret) - return ret; + /* + * Bootstrap page table lookup. + */ + if (bar == 3) { + ret = nouveau_gpuobj_new(nv_object(priv), NULL, + (bar_len >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &vm->pgt[0].obj[0]); + vm-&g...

On Sat, Apr 18, 2015 at 12:37 AM, Terje Bergstrom <tbergstrom at nvidia.com> wrote: > > On 04/17/2015 02:11 AM, Alexandre Courbot wrote: >> >> Tracking the PDE and PTE of each memory chunk can probably be avoided >> if you change your unmapping strategy. Currently you are going through >> the list of nvkm_vm_bp_list, but you know your PDE and PTE are always

Hi, Robert, I found out another confusing code snippet: in void xi_invl_mfn(struct domain *d, unsigned long mfn) if (ext && pfn < ext->large_page_aligned_size) According to the code, it should be if (ext && (pfn>>SPT_ENTRIES_ORDER) < ext->large_page_aligned_size) If I made any mistake, please point it out.