Displaying 3 results from an estimated 3 matches for "perfsuite".
2008 Sep 30
1
[LLVMdev] Hi Cache Miss and Branch Misprediction
...performance counter registers
directly (LLVM supports inline assembly).
If you want to instrument code that is not visible at the LLVM IR level
(e.g., cache misses due to register spills), then you'd need to modify
the code generator, I believe.
You may want to check this resource
(http://perfsuite.ncsa.uiuc.edu/publications/LJ135/t1.html) for
information on software you can use to read performance counters on Linux.
-- John T.
> But all this has given me a quite a bit of knowledge.Wow!!!
>
> Thank you
> Best
> Ketan
> ----- Original Message -----
> From: "Overmin...
2008 Sep 30
0
[LLVMdev] Hi Cache Miss and Branch Misprediction
Thanx a lot Guys!!
But i have to do this online and and use it to do some kind code transformation. Its for a different project.
But all this has given me a quite a bit of knowledge.Wow!!!
Thank you
Best
Ketan
----- Original Message -----
From: "OvermindDL1" <overminddl1 at gmail.com>
To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
Sent: Monday,
2008 Sep 30
2
[LLVMdev] Hi Cache Miss and Branch Misprediction
On Mon, Sep 29, 2008 at 6:30 PM, Mike Stump <mrs at apple.com> wrote:
> /* snip */
AMD's CodeAnalyst is free and quite wonderful at this job. Shows
details about just about anything the CPU reports (and on newer AMD
CPU's there is an even more ridiculous amount of information) about
every little function call, time they took, multiple profiling modes,
etc...