search for: perfc_incr

...en/arch/x86/mm.c 2007-03-27 10:31:15.000000000 +0200 +++ 2007-03-19/xen/arch/x86/mm.c 2007-03-27 10:32:56.000000000 +0200 @@ -1969,6 +1969,8 @@ int do_mmuext_op( if ( unlikely(!guest_handle_is_null(pdone)) ) (void)copy_from_guest(&done, pdone, 1); } + else + perfc_incr(calls_to_mmuext_op); if ( unlikely(!guest_handle_okay(uops, count)) ) { @@ -2223,6 +2225,8 @@ int do_mmuext_op( UNLOCK_BIGLOCK(d); + perfc_add(num_mmuext_ops, i); + out: /* Add incremental work we have done to the @done output parameter. */ if ( unlikely(!guest_h...

...xr/source/xen/arch/x86/mm.c?a=x86_64#L3007> int rc <http://lxr.xensource.com/lxr/ident?a=x86_64;i=rc> = 0; 3008 <http://lxr.xensource.com/lxr/source/xen/arch/x86/mm.c?a=x86_64#L3008> 3009 <http://lxr.xensource.com/lxr/source/xen/arch/x86/mm.c?a=x86_64#L3009> perfc_incr <http://lxr.xensource.com/lxr/ident?a=x86_64;i=perfc_incr>(calls_to_update_va); 3010 <http://lxr.xensource.com/lxr/source/xen/arch/x86/mm.c?a=x86_64#L3010> 3011 <http://lxr.xensource.com/lxr/source/xen/arch/x86/mm.c?a=x86_64#L3011> if ( unlikely <http://lxr.xensource.com/lx...

...GS_IF) || + (regs->error_code & PFEC_reserved_bit) ) return 0; if ( unlikely(IN_HYPERVISOR_RANGE(addr)) ) @@ -1101,6 +1116,8 @@ asmlinkage void do_page_fault(struct cpu if ( likely((fixup = search_exception_table(regs->eip)) != 0) ) { perfc_incr(copy_user_faults); + if ( unlikely(regs->error_code & PFEC_reserved_bit) ) + reserved_bit_page_fault(0, addr, regs); regs->eip = fixup; return; } _______________________________________________ Xen-devel mailing list Xen-dev...

...gt;domain->domain_id, v->vcpu_id, va, regs->error_code, regs->rip); +#elif defined(__i386__) + SHADOW_PRINTK("d:v=%u:%u va=%#lx err=%u\n", + v->domain->domain_id, v->vcpu_id, va, regs->error_code); +#endif /* __i386__ */ perfc_incr(shadow_fault); -- TAMURA, Yoshiaki NTT Cyber Space Labs OSS Computing Project Kernel Group E-mail: tamura.yoshiaki@lab.ntt.co.jp TEL: +81-46-859-2771 FAX: +81-46-855-1152 Address: 1-1 Hikarinooka, Yokosuka Kanagawa 239-0847 JAPAN _______________________________________________ Xen-devel maili...

...eturn; +#endif + if ( !opt_x2apic ) { if ( !x2apic_enabled ) diff -r 02c0af2bf280 xen/arch/x86/x86_32/domain_page.c --- a/xen/arch/x86/x86_32/domain_page.c Mon Jan 17 18:05:52 2011 +0000 +++ b/xen/arch/x86/x86_32/domain_page.c Wed Jan 19 03:24:16 2011 -0500 @@ -53,6 +53,8 @@ perfc_incr(map_domain_page_count); v = mapcache_current_vcpu(); + /* Prevent vcpu pointer being used before initialize. */ + ASSERT((unsigned long)v != 0xfffff000); dcache = &v->domain->arch.mapcache; vcache = &v->arch.mapcache; _______________________________________...

...vm/vmx/vmx.c =================================================================== --- hv.orig/xen/arch/x86/hvm/vmx/vmx.c +++ hv/xen/arch/x86/hvm/vmx/vmx.c @@ -2617,6 +2617,13 @@ asmlinkage void vmx_vmexit_handler(struc break; } + case EXIT_REASON_PAUSE_INSTRUCTION: + { + perfc_incr(ple_exits); + do_sched_op_compat(SCHEDOP_yield, 0); + break; + } + default: exit_and_crash: gdprintk(XENLOG_ERR, "Bad vmexit (reason %x)\n", exit_reason); Index: hv/xen/include/asm-x86/hvm/vmx/vmcs.h =====================================================...

This set of patches converts the way frames gets created from using PUSHes/POPs to using MOVes, thus allowing (in certain cases) to avoid saving/restoring part of the register set. While the place where the (small) win from this comes from varies between CPUs, the net effect is a 1 to 2% reduction on a combined interruption entry and exit when the full state save can be avoided. 1: use MOV

...c = -EFAULT; + else if ( test_bit(_MCSF_call_preempted, &mcs->flags) ) + { +@@ -93,6 +101,9 @@ do_multicall( + guest_handle_add_offset(call_list, 1); + } + ++ if ( unlikely(disp == mc_preempt) && i < nr_calls ) ++ goto preempted; ++ + perfc_incr(calls_to_multicall); + perfc_add(calls_from_multicall, i); + mcs->flags = 0; +--- xen-4.4.1.orig/xen/include/asm-arm/multicall.h ++++ xen-4.4.1/xen/include/asm-arm/multicall.h +@@ -1,7 +1,11 @@ + #ifndef __ASM_ARM_MULTICALL_H__ + #define __ASM_ARM_MULTICALL_H__ + +-extern void do_multic...

Moritz Muehlenhoff writes ("Re: Xen package security updates for jessie 4.4, XSA-213, XSA-214"): > On Thu, May 04, 2017 at 05:06:07PM +0100, Ian Jackson wrote: > > I have fixed these in stretch but the jessie package remains unfixed. > > I think I may be able to find some backports somewhere. Would that be > > useful ? Is anyone else working on this ? > >

I am confused with a problem: I have a blade with 64 physical CPUs and 64G physical RAM, and defined only one VM with 1 CPU and 40G RAM. For the first time I started the VM, it just took 3s, But for the second starting it took 30s. After studied it by printing log, I have located a place in the hypervisor where cost too much time, occupied 98% of the whole starting time. xen/common/page_alloc.c

...); - cpumask_clear_cpu(cpu, &call_data.selected); - } - else - { - mb(); - cpumask_clear_cpu(cpu, &call_data.selected); - (*func)(info); - } - - irq_exit(); -} - void call_function_interrupt(struct cpu_user_regs *regs) { ack_APIC_irq(); perfc_incr(ipis); - __smp_call_function_interrupt(); + smp_call_function_interrupt(); } diff --git a/xen/common/Makefile b/xen/common/Makefile index 8a0c506..0dc2050 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -26,6 +26,7 @@ obj-y += schedule.o obj-y += shutdown.o obj-y += softirq.o...

...uest trying to access? */ gfn = guest_l1e_get_gfn(gw.eff_l1e); gmfn = vcpu_gfn_to_mfn(v, gfn); mmio = (is_hvm_domain(d) && paging_vcpu_mode_translate(v) && mmio_space(gfn_to_paddr(gfn))); if ( !mmio && !mfn_valid(gmfn) ) { perfc_incr(shadow_fault_bail_bad_gfn); SHADOW_PRINTK("BAD gfn=%"SH_PRI_gfn" gmfn=%"PRI_mfn"\n", gfn_x(gfn), mfn_x(gmfn)); goto not_a_shadow_fault; } _______________________________________________ Xen-devel mailing list Xen-devel@lists.xe...

From: Yang Zhang <yang.z.zhang@Intel.com> The follwoing patches are adding the Posted Interrupt supporting to Xen: Posted Interrupt allows vAPIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu. Then the vcpu will handle this

Attached are the patches to support super page with EPT. We only support 2M size. And shadow may still work fine with 4K pages. The patches can be split into 3 parts. Apply order is as attached. tool.diff To allocate 2M physical contiguous memory in guest except the first 2M and the last 2M. The first 2M covers special memory, and Xen use the last few pages in guest memory to do special

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See