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From: Jim Grosbach [mailto:grosbach at apple.com] Sent: Friday, October 25, 2013 4:31 PM To: David Peixotto Cc: Renato Golin; LLVM Dev Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. -- Qu...

On Oct 25, 2013, at 6:14 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Friday, October 25, 2013 4:31 PM > To: David Peixotto > Cc: Renato Golin; LLVM Dev > Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler >...

Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From: Renato Golin [mailto:renato.golin at linaro.org] Sent: Friday, October 25, 2013 1:11 PM To: David Peixotto Cc: LLVM Dev; Logan Chien; Gabor Ballabas; Rafael Espíndola; Richard Barton; Amara Emerson Subject: Re: Add support for ldr pseudo instruction in ARM integrated assembler On 25 October 2013 18:33, David Peixotto <dpeixott at codeaurora.org> wrote: Both armasm and gnu as support an ldr ps...

On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > > > From: Renato Golin [mailto:renato.golin at l...

...g `=`. The updated patch is attached. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: Amara Emerson [mailto:amara.emerson at arm.com] > Sent: Tuesday, November 12, 2013 5:43 AM > To: 'David Peixotto' > Cc: llvmdev at cs.uiuc.edu > Subject: RE: [LLVMdev] Implementing the ldr pseudo instruction in ARM > integrated assembler > > Hi David, > > Thanks for your efforts here. I have a few comments on your patch, > although I realise it's still a work in progress. &gt...

...g discussion to llvm-commits now that I have a more developed implementation: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20131111/195401. html > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of David Peixotto > Sent: Tuesday, November 12, 2013 11:09 AM > To: 'Amara Emerson' > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Implementing the ldr pseudo instruction in ARM > integrated assembler > > Hi Amara, > > Thanks for your suggestions. I have made the changes y...

On Sep 6, 2012, at 4:40 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > -----Original Message----- > From: Bob Wilson [mailto:bob.wilson at apple.com] > Sent: Thursday, September 06, 2012 3:39 PM > To: David Peixotto > Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs...

> -----Original Message----- > From: Bob Wilson [mailto:bob.wilson at apple.com] > Sent: Friday, September 07, 2012 10:57 AM > To: David Peixotto > Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Unaligned vector memory access for ARM/NEON. > > > On Sep 6, 2012, at 4:40 PM, David Peixotto <dpeixott at codeaurora.org> > wrote: > > &g...

Hi David, Thanks for your efforts here. I have a few comments on your patch, although I realise it's still a work in progress. +class ConstantPool { + MCSymbol *Label; + typedef std::vector<const MCExpr*> EntryVecTy; Use a SmallVector here? + MCSymbol *getLabel() {return Label;} + size_t getNumEntries() {return Entries.size();} + const MCExpr *getEntry(size_t Num) {return

Hi, On Sat, Oct 22, 2011 at 12:03 PM, David Peixotto <dmp at rice.edu> wrote: > I'm having a problem with the code generated for the popcnt intrinsic on MacOSX. The `llc` program will generate the assembly just fine, but the assembler fails with the error: > >   suffix or operands invalid for `popcnt' > > The problem is t...

"David Peixotto" <dpeixott at codeaurora.org> writes: > I think the main benefit of a scheme like this would be that a pull > request tells a code owner which patches require their attention. As a > contributor it would be nice to see your patch in a queue somewhere > rather than just be bu...

On Sep 7, 2012, at 4:46 PM, David Peixotto <dpeixott at codeaurora.org> wrote: >> Note that this won't work on big-endian targets where changing the >> vld1/vst1 element size actually changes the behavior of the instructions. > > Ok, so would it be best to put an explicit test for endianess in the code? > The...

"David Peixotto" <dpeixott at codeaurora.org> writes: > I'd like to build llvm with assertions enabled, but build clang with > assertions disabled. In other words, I'd like lvm in Release+Asserts mode, > but clang in Release mode. > > Is it possible to do this with one top level...

I'm having a problem with the code generated for the popcnt intrinsic on MacOSX. The `llc` program will generate the assembly just fine, but the assembler fails with the error: suffix or operands invalid for `popcnt' The problem is that the mac assembler does not support length suffixes on the popcnt instruction (e.g. {w,l,q} suffixes). GCC handles this by not adding the suffixes to

Both armasm and gnu as support an ldr pseudo instruction for loading constants that lowers to either a mov, movn, or a pc-relative ldr from the constant pool. It would be great if the llvm integrated assembler could support this feature as well. For example, using gnu as to compile this code: .text foo: ldr r0, =0x1 ldr r0, =-0x1 ldr r0, =0x1000001 ldr r0, =bar

On 25 October 2013 18:33, David Peixotto <dpeixott at codeaurora.org> wrote: > Both armasm and gnu as support an ldr pseudo instruction for loading > constants that lowers to either a mov, movn, or a pc-relative ldr from the > constant pool. It would be great if the llvm integrated assembler could > support this feature...

Hi, I'd like to build llvm with assertions enabled, but build clang with assertions disabled. In other words, I'd like lvm in Release+Asserts mode, but clang in Release mode. Is it possible to do this with one top level configure/make command? If not, any idea how much work would it be to add this feature to llvm? I'm not very familiar with llvm's build system. Thanks!

-----Original Message----- From: Bob Wilson [mailto:bob.wilson at apple.com] Sent: Thursday, September 06, 2012 3:39 PM To: David Peixotto Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Unaligned vector memory access for ARM/NEON. On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the s...

...be any need to output an object file. Just checking the .s output from the asm streamer should be sufficient here. These tests are very linux specific, including names and relocation type information. What happens when compiling on or for other platforms? -Jim On Nov 15, 2013, at 6:05 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Moving discussion to llvm-commits now that I have a more developed > implementation: > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20131111/195401. > html > > >> -----Original Message----- >> From: llvmdev-...

On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the same issue with generating vector loads/stores for vectors > with less than word alignment. It seems we took a similar approach to > solving the problem by modifying the logic in allowsUnalignedMemoryAccesses....