Displaying 5 results from an estimated 5 matches for "pdiv".
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pdev
2005 May 06
1
Again on DC prediction
Reading the source code i noted the zeroing of the LASTDC array after
each plane (Y,U,V) in the DC prediction function.
Perhaps i missed this in the specification, but in the chapter 7.8.2
(Inverting the DC prediction precess) i don't find this wrote down.
Can someone explain me this?
Thanks in advance
-Marco Bagnaresi
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new
camera. The previous model (Elphel 313 - http://www.elphel.com,
https://sourceforge.net/projects/elphel) had smaller FPGA and was
able to produce just motion JPEG utilizing 97% of the resources. The
new (model 333) camera uses 3 times bigger FPGA (and also faster), it
also has increased frame buffer and system memory.
2004 Sep 07
3
FPGA implementation in the camera
I'm considering implementing the Theora format in the FPGA of the new
camera. The previous model (Elphel 313 - http://www.elphel.com,
https://sourceforge.net/projects/elphel) had smaller FPGA and was
able to produce just motion JPEG utilizing 97% of the resources. The
new (model 333) camera uses 3 times bigger FPGA (and also faster), it
also has increased frame buffer and system memory.
2011 Mar 24
1
Various typo in spec
...]x ).
E. Assign MVY2 the value
|MVECTS[bi ]y | ? sign(MVECTS[bi ]y ).
As MVECTS are integer, floor and ciel functions give the same result.
I do not understand. Maybe MVECTS[bi ] should be replaced by MVECTS[bi ]
/2 in all these expressions ?
* Few typos :
in section 7.8.1
Variables used :
PDIV (...) The valud -> the valu*e*
mbi->mb*j* (...) The index ... block bj
7. If block bi is not along the *the* bottom
in table 7.47 :
p[0] p[1] p[2] p[3] w[3] w[1] w[2] w[3] -> p[0] p[1] p[2] p[3] w[*0*]
w[1] w[2] w[3]
Regards
J.F.
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2016 Jun 01
15
[PATCH 00/15] clk/tegra: improve code and add DFS support
This series adds support for GM20B PLL's Maxwell features, namely glitchless
switch and (more importantly) DFS support. DFS lets the PLL lower its output
speed according to input current variations, making the clock more stable and
allowing it to run safely at lower voltage.
All GM20B additions are done in the last patch, which consequently ends up
being considerably big ; fortunately, it