search for: pdep

I have a group of students working with me on some LLVM projects related to our Parabix research. One interesting issue that has come up for us is code generation support for the Haswell new instructions pext and pdep. These instructions shuffle bits within a 64-bit word, either gathering all selected bits to the beginning (pext) or scattering some initial bits throughout (pdep). A natural model for this is to use shufflevector on v32i1 and v64i1 vectors. We've got some preliminary notes here: http://pa...

Hello, I’m not sure if this is the right place to ask beginner questions. If not, please direct me to the appropriate place. I’m writing my first llvm program and I’m trying to call an intrinsic, but failing. So far this is what I have: declare ccc i32 @llvm.x86.bmi.pdep.32(i32, i32) @.str2 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 declare i32 @printf(i8*, ...) nounwind ; Definition of main function define i32 @main() { %res = call ccc i32 (i32, i32) @llvm.x86.bmi.pdep.32( i32 1, i32 1 ) %a = alloca i32, align 8 %1 = load i32...

...ot sure if this is the right place to ask beginner questions. > > If not, please direct me to the appropriate place. > > I’m writing my first llvm program and I’m trying to call an intrinsic, > but failing. > > So far this is what I have: > > declare ccc i32 @llvm.x86.bmi.pdep.32(i32, i32) > > @.str2 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 > > declare i32 @printf(i8*, ...) nounwind > > ; Definition of main function > define i32 @main() { > %res = call ccc i32 (i32, i32) @llvm.x86.bmi.pdep.32( i32 1, i32 1 ) > &...

...o ask beginner questions. >> >> If not, please direct me to the appropriate place. >> >> I’m writing my first llvm program and I’m trying to call an intrinsic, >> but failing. >> >> So far this is what I have: >> >> declare ccc i32 @llvm.x86.bmi.pdep.32(i32, i32) >> >> @.str2 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 >> >> declare i32 @printf(i8*, ...) nounwind >> >> ; Definition of main function >> define i32 @main() { >> %res = call ccc i32 (i32, i32) @llvm.x86.bm...

...t expression.c:520 No locals. #1 binop_expr_print (expr=0x47a8a13610) at expression.c:532 No locals. #2 0x00000047a6a05888 in trace_print_packet (nlt=nlt at entry=0x47a8a22050) at netlink.c:2380 stmts = {next = 0x47a8a0cc90, prev = 0x47a8a12a90} pctx = {pbase = PROTO_BASE_INVALID, pdep = 0x0, prev = 0x0} ctx = {family = 5, protocol = {{location = {indesc = 0x0, {{token_offset = 0, line_offset = 0, first_line = 0, last_line = 0, first_column = 0, last_column = 0}, {nle = 0x0}}}, desc = 0x0, offset = 0}, {location = {indesc = 0x0, {{token_offset = 0, line_offset = 0, first_...

Thanks for writing this up. I'd like to have this intrinsic too. Another argument for having the intrinsic is shown in PR37426: https://bugs.llvm.org/show_bug.cgi?id=37426 Vectorization goes overboard because the throughput cost model used by the vectorizers doesn't match the 6 IR instructions that correspond to 1 x86 rotate instruction. Instead, we have: $ opt 37426prevectorize.ll -S

Hi everyone! I recently ran into some interesting issues with generation of rotate instructions - the details are in the bug tracker (https://bugs.llvm.org/show_bug.cgi?id=37387 and related bugs) for those interested - and it brought up the issue of rotates in the IR again. Now this is a proposal that has been made (and been rejected) several times, but I've been told that this time round we