Displaying 3 results from an estimated 3 matches for "pcie_pm_reg".
2019 Sep 27
2
[RFC PATCH] pci: prevent putting pcie devices into lower device states on certain intel bridges
Fixes runpm breakage mainly on Nvidia GPUs as they are not able to resume.
Works perfectly with this workaround applied.
RFC comment:
We are quite sure that there is a higher amount of bridges affected by this,
but I was only testing it on my own machine for now.
I've stresstested runpm by doing 5000 runpm cycles with that patch applied
and never saw it fail.
I mainly wanted to get a
2019 Sep 27
0
[RFC PATCH] pci: prevent putting pcie devices into lower device states on certain intel bridges
...fect. Without the specifics, this is just a band-aid.
I don't see any relevant requirements in the _OFF description, but I
don't know much about ACPI power control.
Your script allows several scenarios; I *guess* the one that causes
the problem is:
- write 3 (D3hot) to GPU PowerState (PCIE_PM_REG == 0x64, I assume
PM Capability Control Register)
- write 3 (D3hot) to bridge PowerState (0x84, I assume PM Capability
Control Register)
- run _OFF on the power resource for the bridge
>From your script I assume you do:
- run _ON on the power resource for the bridge
- write 0 (...
2019 Sep 27
2
[RFC PATCH] pci: prevent putting pcie devices into lower device states on certain intel bridges
...tel is still pending.
> I don't see any relevant requirements in the _OFF description, but I
> don't know much about ACPI power control.
>
> Your script allows several scenarios; I *guess* the one that causes
> the problem is:
>
> - write 3 (D3hot) to GPU PowerState (PCIE_PM_REG == 0x64, I assume
> PM Capability Control Register)
correct
> - write 3 (D3hot) to bridge PowerState (0x84, I assume PM Capability
> Control Register)
correct, but this seems to be fine and doesn't fix the issue if that
part is skipped
> - run _OFF on the power resou...