Displaying 5 results from an estimated 5 matches for "pcicfg".
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pci_cfg
2013 Sep 30
2
known MSI errata?
Hi,
recently we tried to enable MSI interrupts with nouveau. Unfortunately
there have been some reports of things failing with certain cards, where
it isn't entirely clear if this is a GPU errata or some other component
in the PCIe chain failing.
Could you perhaps investigate if there are any known Nvidia GPU erratas
with regard to MSI interrupts, or maybe tell us the generations of cards
2013 Oct 24
2
known MSI errata?
...mentation and source code, and found a couple
> of things that are probably interesting to you:
> - For all pre-Fermi GPUs, we use a write through PCI config space to the "EOI"
> register to rearm the MSI interrupt after servicing it, rather than a write
> through the MMIO pcicfg shadow region in the GPU's PCI BAR0 window at offset
> 0x88000. (This was actually originally implemented for NV4x, so you'll
> probably want to do that there as well.)
Hm, I recently discovered this while looking for the errata myself,
but it seems you guys only do it on G80/G84...
2006 Oct 31
0
5049969 Make efcode'' PCI configurator as the default configurator for SPARC platforms (fix unref)
Author: kini
Repository: /hg/zfs-crypto/gate
Revision: 239e64d12f9aeefee74374c799a32a2ab5ddff8c
Log message:
5049969 Make efcode'' PCI configurator as the default configurator for SPARC platforms (fix unref)
Files:
create: deleted_files/usr/src/uts/sparc/pcicfg/Makefile
delete: usr/src/uts/sparc/pcicfg/Makefile
2013 Oct 24
0
known MSI errata?
...ed our internal documentation and source code, and found a couple
of things that are probably interesting to you:
- For all pre-Fermi GPUs, we use a write through PCI config space to the "EOI"
register to rearm the MSI interrupt after servicing it, rather than a write
through the MMIO pcicfg shadow region in the GPU's PCI BAR0 window at offset
0x88000. (This was actually originally implemented for NV4x, so you'll
probably want to do that there as well.) It seems that this was done to
avoid a hardware bug that may cause the EOI write to be dropped, blocking
all further...
2013 Oct 24
0
known MSI errata?
...code, and found a couple
> > of things that are probably interesting to you:
> > - For all pre-Fermi GPUs, we use a write through PCI config space to the "EOI"
> > register to rearm the MSI interrupt after servicing it, rather than a write
> > through the MMIO pcicfg shadow region in the GPU's PCI BAR0 window at offset
> > 0x88000. (This was actually originally implemented for NV4x, so you'll
> > probably want to do that there as well.)
> Hm, I recently discovered this while looking for the errata myself,
> but it seems you guys o...